More hits to the heart for the 4 PE's CPU fans (CELL)

[V3]

Forgive my ignorance, but what's with the dual XDRRAM blocks for each CELL? What's the significance of that?

Each cell has dual XDR controller for a total of 25.6GB/s bandwidth.

 

[j^aws]

1 EE+GS core(small square)+ 2 cell ?

[2*CELL] + [IOP + [EE+GS]]

Nah...too much silicon?

EDIT: Could be for dev workstations now at 90nm, then later shrink to 65nm for PS3?

 

[j^aws]

Look at long strip between CELLs again...

There are 3 solder bump areas...i.e.

1. For Rambus 32MB RDRAM for PS2?
2. For connection to I/O bus?
3. For connection to CELL?

[IOP + [EE+GS]] ?

 

[version]

in ps3 will be 1 cell+1 gpu , because for 2 cells+1gpu must have 1 switch , sorry this is real logic

 

[j^aws]

Ignore 2 CELLs for the time being...Is that IOP with 3 solder bump areas?

 

[Brimstone]

So in the future will STI end up using something similar to "Proximity Communication" like Sun has?

 

[j^aws]

This isn't a test strip...It's an IC with 3 solder pad areas? I.e. the IOP?

 

[BOOMEXPLODE]

Isn't it a little big for an IO processor? It has almost as much surface area as Cell does. Could be an EE+GS, but that still wouldnt account for it's size relative to Cell.

 

[j^aws]

Isn't it a little big for an IO processor? It has almost as much surface area as Cell does. Could be an EE+GS, but that still wouldnt account for it's size relative to Cell.

It's an IC at least...I'm sure because of the 3 areas of solder pads???

IOP=Sound/Media proc/EE+GS+other PS2 IC-RAM/Blu-ray codec/wi-fi/network etc...

 

[Shinjisan]

in ps3 will be 1 cell+1 gpu , because for 2 cells+1gpu must have 1 switch , sorry this is real logic

No a 2 Cell CPU doesn't need a switch.A 4 Cell CPU would.
The GPU is external and uses the FelxIO interface to communicate.

 

[j^aws]

in ps3 will be 1 cell+1 gpu , because for 2 cells+1gpu must have 1 switch , sorry this is real logic

No a 2 Cell CPU doesn't need a switch.A 4 Cell CPU would.
The GPU is external and uses the FelxIO interface to communicate.

True...you need switch for 4 CELLs...but not 2 CELLs...

 

[j^aws]

I/O <--->[IOP]<=>[CELL]<=>[CELL]<=>[GPU]---> Output

Possible but unlikely...

 

[version]

cell and GPU connecting by FlexIO

i think this ^^^ wafer will be for workstation, 2 cell+IO with 32MB edram shared memory

 

[j^aws]

cell and GPU connecting by FlexIO

i think this ^^^ wafer will be for workstation, 2 cell+IO with 32MB edram shared memory

Where's the eDRAM, on the IOP? Why?

 

[version]

cell and GPU connecting by FlexIO

i think this ^^^ wafer will be for workstation, 2 cell+IO with 32MB edram shared memory

Where's the eDRAM, on the IOP? Why?

 

[j^aws]

cell and GPU connecting by FlexIO

i think this ^^^ wafer will be for workstation, 2 cell+IO with 32MB edram shared memory

Where's the eDRAM, on the IOP? Why?

That doesn't look like eDRAM...not uniform enough...check the GS die pics...and why would you need eDRAM on the IOP anyway?

 

[version]

if cells's buses are busy then store datas in edram, i mean

 

[Quaz51]

this Wafer is a 10S process and the 10S (90nm),11S (65nm) ,12S (45nm) process (SOI,lowK) developed by STI for the Cell is not a eDRAM process, i think
the eDRAM+logic process is developed by Sony and Toshiba (for the GPU probably) and named CMOS4 (90nm> PSP chip and EE+GS chip), CMOS5 (65nm > PS3 GPU?), CMOS6 (45nm, PS3 GPU evolution) and is not SOI

 

[j^aws]

if cells's buses are busy then store datas in edram, i mean

Okay, that still sounds messy though...

The image still doesn't look like eDRAM because I can't see large banks of uniform eDRAM on the pic where you've highlighted eDRAM...see die of GS...

 

[version]

if cells's buses are busy then store datas in edram, i mean

Okay, that still sounds messy though...

The image still doesn't look like eDRAM because I can't see large banks of uniform eDRAM on the pic where you've highlighted eDRAM...see die of GS...

wher is GS's wafer? link? please