More hits to the heart for the 4 PE's CPU fans (CELL)
- Thread starter Panajev2001a
- Start date
version said:
Well then go back to one of the 4 million Cell threads and look for the answer to the same question. It wasn't even 2 weeks ago. It's in the thread with the first pic of Cell.
Jaws said:
It's like.. the first Cell chips that have been produced in... EVER. So i guess it's justified.
But i'm beginning to understand version's question. I think he's trying to say, in his very broken english, that there is one circuity bit for each pair of Cell (if you notice). So i think he's thinking they're testing how 2 chips work at a time, fuelling rumours of a double Cell configuration for PS3. I say, let's wait and see.
Theres space between each Cell and "the other Chip". Why would they do such a thing if its not for being able to seperate them.
To get a Dual Setup Sony would still need to wire the connections, so they could aswell place 2 seperate Cell-Dies beneath each other AND have higher yields (not having to throw away a 2 Cell-Package if one is defect).
Assuming a Dual-setup because of that wafer is nonsense, not that there coldnt be a Dual-setup, but that picture aint giving arguments for or against it.
To get a Dual Setup Sony would still need to wire the connections, so they could aswell place 2 seperate Cell-Dies beneath each other AND have higher yields (not having to throw away a 2 Cell-Package if one is defect).
Assuming a Dual-setup because of that wafer is nonsense, not that there coldnt be a Dual-setup, but that picture aint giving arguments for or against it.
london-boy said:Jaws said:
It's like.. the first Cell chips that have been produced in... EVER. So i guess it's justified.
But i'm beginning to understand version's question. I think he's trying to say, in his very broken english, that there is one circuity bit for each pair of Cell (if you notice). So i think he's thinking they're testing how 2 chips work at a time, fuelling rumours of a double Cell configuration for PS3. I say, let's wait and see.
yeah, i learning engilsh from processor manuals , sorry
MechanizedDeath
Regular
Which side of the chip has the FlexIO interface? Isn't that on the side with the SPEs? Isn't that the opposite side of that circuit? I can't tell how the chip is oriented, but that's what it looks like to me. Looks like that circuit is on the side with the PPE rather than the SPEs, so it'll be connecting to the memory interface. PEACE.
zidane1strife
Banned
O/T semi-related question.
I forgot, why do they make the wafers round instead of square?
I forgot, why do they make the wafers round instead of square?
Is it confirmed fact or just a rumor that the area is used for testing ?
Wouldnt it be more likely that the testing circuitry is required in much lower quantities and being factured seperate from the Cell-Wavers - I mean how the hell do the know the testing circuitry itself is good (it has not exactly a insignificant size) ?
Prolly a Chip they will need in a fixed ratio to the manufactured Cells, Cell-Workstation-Northbridge for example( assuming a 2 Cell setup, with alot DDR-RAM through the NB ).
Wouldnt it be more likely that the testing circuitry is required in much lower quantities and being factured seperate from the Cell-Wavers - I mean how the hell do the know the testing circuitry itself is good (it has not exactly a insignificant size) ?
Prolly a Chip they will need in a fixed ratio to the manufactured Cells, Cell-Workstation-Northbridge for example( assuming a 2 Cell setup, with alot DDR-RAM through the NB ).
RichardCypher101
Newcomer
zidane1strife said:
From cpiasminc of PSINext.com:
-Rich
RichardCypher101
Newcomer
Couldnt resist.
-Rich
-Rich