Larrabee at Siggraph
- Thread starter nAo
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All the talk prior to this about why GPUs still run at most 1 tri/clk seemed to revolve around concerns about the expectation that rasterization be done serially.
Can the setup workload be distributed to multiple units or cores, where we wouldn't expect the results in one area to invalidate the parallel work of all those cores that happen to follow later in rasterization order?
As for atomic operations, both GT200 and RV770 now have infrastructure in place that would either allow them or would in a generation's time implement them if they aren't already there.
Yes, but nevertheless Intel sees this as a 'transitional period', even if this period can last a few years. OGL/D3D is where they start from, not what they're going to.
Perhaps a few brave developers is all it takes.
Currently there's only a handful of engines powering the most successful games. The rest just license the technology and expand on it.
I think if ID, Valve, Epic and CryTek build their own renderers, you'll have a big portion of the games market covered.
There could also be room for new middleware players. There's plenty of people that can write a good software renderer. That's something completely different from designing and marketing a successful game.
Jawed
Legend
Well the irony being that when you're filling your "irregular shadow map" burning up all that triangle-rate, the only other thing you'll be doing is a funky rasterisation calculation (which is easily parallelisable) and some trivial Z comparisons.It's never enough, NEVER
Especially if you have no resources left to do anything else!
I'm most interested now in what their effective dynamic branching coherency is going to be. It would be really nice if it turns out to be a quad
Though I wouldn't be surprised if it's actually 4 quads.I suppose there's a decent chance the software could take portions of shader that consist of DB and vectorise those instructions, making coherency quad-sized instead of 4-quad. Outside of DB they could then use NVidia's serial-scalar approach to maximise the utilisation of instructions that are smaller than vec4.
Jawed
http://www.intel.com/pressroom/archive/releases/20080804fact.htm?cid=rss-90004-c1-210459
But its still not there yet.
Intel's PR Not Geo Being Bad Yet Again said:
But its still not there yet.
Cheers
Thoburn said:
AVX will bring 8 wide vector ALU's to Sandybridge, right? And that compares to 4 wide on Core2/Nehalem?
I guess with 8 cores and a decent clock speed thats still nothing to sniff at but you can see how Larrabee will be in a different league.
What i'm waiting for are the Sandybridge/Larrabee mixed cores. Say a quad Sandybridge combined with 24 Larrabee cores
So, to cut to the chase, they are claiming 10-25 "Larrabee cores" at 1GHz to run FEAR at 1600x1200 60fps with "4 samples" (is that 4xaa or 4xaf or what?)
Well, I guess it'd be more accurate to say they are claiming 25 1GHz cores to keep performance at a minimum of 60fps.
Well, I guess it'd be more accurate to say they are claiming 25 1GHz cores to keep performance at a minimum of 60fps.
I think looking at the chart, if it's accurate, performance should go above 60fps with 25 1Ghz cores. Some of there sample frames need only 5 cores, for example, to be done in 1/60th of a second...for most of those sample frames the numbers required are far less than 25.
So maybe it's more accurate to say that 25 is needed to prevent it dipping below 60fps.
If I'm understanding it right..
edit - also, can I post the chart?
Nearly all of the preview sites nabbed images from this paper. Staff?
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