Intel Xe Architecture for dGPUs

Discussion in 'Architecture and Products' started by DavidGraham, Dec 12, 2018.

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  1. Digidi

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    „Spit out„ sounds More like after all things done you get 2 out. @Ryan Smith can you clear this?
     
  2. Megadrive1988

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  3. Ryan Smith

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    My understanding is that it's after culling, so 2 backface culled primitives per clock.

    For reference, here's the exact text on the spec for Gen11, which was 1/cycle: "Primitive / Clock (backface Cull - strips)"
     
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  4. Digidi

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    Thank you @Ryan Smith. Sorry but i'm not a native englisch speaker. I don't get it. So this mean after Culling you get 2 Primitives. Does this mean they have 2 Rasterizer? Or is it befor Rasterizer. Thank you in advanced!
     
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  5. CarstenS

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    The rasterizer converts continous geometry information into the pixel raster, hence the name. It's capabilities are mostly measured by how many pixels per clock it puts out, normally not by how many different triangles they can belong to.

    edit: Very late edit after thread split: Please see here as well where I expand a little on what should have been in this very post from the beginning.
     
    #265 CarstenS, Aug 18, 2020
    Last edited: Sep 4, 2020
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  6. BRiT

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  7. Digidi

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    Funny Intel had a tiger lake event with new gpu an here is total silence :)
     
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  8. Malo

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    Yeah. Terrible timing, or maybe on purpose? From the couple of videos I've watched reviewing the presentation, it was a rather pathetic release.

    The start of Gamers Nexus video was rather funny.
     
  9. Leovinus

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    I've certainly been made aware of the Renoir 4800U and how it competes with the 11th gen 11... the 116... Was there a letter in there? 11486Ö? Yea, sounds about right.

    Seriously though. I can't really fathom the potential customer who'd ever go "Oh they're talking shit about the competition, this is a company I can trust to deliver". Then again I'm equally stumped when the same pattern repeats elsewhere, so maybe I'm just not very good at this "human" stuff.

    As to the product, I just want it in testers hands to get an iGPU vs iGPU test done. I'm low-key excited about Xe. More competition in the space will be interesting.
     
  10. sonen

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    Please no memes. Lets stick with benchmarks.

    [​IMG]

    [​IMG]
     
  11. Leovinus

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    Matrox. Now that is a name I've not heard in a long time. A long time.
     
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  12. CarstenS

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    They (also?) use Nvidia chips now, strangely, Nvidia failed to mention this. ;)
     
    #272 CarstenS, Sep 5, 2020
    Last edited: Sep 5, 2020
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  13. Pressure

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    Matrox G400 Max, that brings back memories.
     
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  14. Digidi

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    The Geometry is confusing me on tiger lake. So howmany rasterizer have 1 chiplet now?
     
  15. CarstenS

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    Chiplet? That's AMD.
     
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  16. Digidi

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    Tiger Lake is confusing. I mean the slice but i don't mean the 6 subslices. arggg....
     
  17. CarstenS

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  18. Digidi

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    Thankt you CarstenS! In this picture it looks a little bit strange. You have 3 pixel Backends for 2 Subslices that means normaly that you have also 3 rasterizer?

    [​IMG]
     
  19. 3dilettante

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    There is an argument for there being at least as much pixel throughput in the pixel back end as the rasterizer is capable of emitting. A mismatch wouldn't necessarily break anything, but could lead to underutilization or stalls depending on which way the imbalance goes.
    Having one rasterizer could make it simpler to have mismatched counts, since there's no uncertainty on the part of the rest of the pipeline about which rasterizer is responsible for a given tile. Having multiple rasterizers could make it easier to match the raster/RBE throughput, but depending on how processing is handled it might require extra work or communication between front ends when geometry processing applies to more than one tile (triangle crossing boundaries, tessellation output from one execution unit needing to flow to arbitrary front ends, etc.).
    Being typically at the end, ROPs would have these questions already resolved.

    That seems to be an area of complexity in how AMD managed its multiple rasterizers in past generations. The unification of certain parts of the front end in RDNA may be in part due to improving potential weak points in making multiple rasterizers with mostly equal levels of authority but possibly uneven methods of cooperation.
     
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  20. Digidi

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    #280 Digidi, Sep 15, 2020
    Last edited: Sep 16, 2020
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