Details trickle out on CELL processor...

[j^aws]

http://www.eet.com/semi/news/showArticle.jhtml?articleId=54200580

 

[Qroach]

"The PS3 memory is rumored to be able to transfer around 100 Gbytes/second, which would mean it could process new data at roughly 25 Gflops (at 32 bits) — far from the 1-Tflops number."

I'd really like ot know just how close it will get to the 1 Tflop number hyped a while back.

 

[V3]

According to one of the ISSCC papers on the Cell design, a single chip implements a single processing element.

I want te get my hands on that ISSCC papers. It'll be released later today, so prepare the ninjas

I want to know the die size of that PE, on 90nm.

 

[Vince]

How funny, Look at the difference between what i was going to post and Q did

• Giving scale to the performance targets for the project, one of the ISSCC papers puts the performance of the streaming-processor SRAM at 4.8 GHz

  
  

  "The PS3 memory is rumored to be able to transfer around 100 Gbytes/second, which would mean it could process new data at roughly 25 Gflops (at 32 bits) — far from the 1-Tflops number." - Zimmons, UNC

Also, I wouldn't put much faith in Mr. Zimmon's comments, he's doing the same bandwith/flop math that Deadmeat used a year or so ago. External bandwith isn't an indication of calulation ability (ala contemporary GPUs).

 

[Vince]

I want to know the die size of that PE, on 90nm.

Same, I'd like to see how far we (or I) was with: On the Feasibility of the Broadband Engine So far it looks excellent from that article, 128KB SRAM @ 4.8GHz and 128*128bit registers per S|APU, with 4 FPU & 4 FXU's per S|APU, upto 8 S|APUs per PE, 6.4GHz RaZor interconnections (with and concurrency will be interesting). Looks to be DMAC heavy to arbitrate, which a few of us have emphasised.

Patent personified so far.

 

[Fafalada]

"The PS3 memory is rumored to be able to transfer around 100 Gbytes/second, which would mean it could process new data at roughly 25 Gflops (at 32 bits) — far from the 1-Tflops number."

It's official - Deadmeat = Mr.Zimmon.

I'd really like ot know just how close it will get to the 1 Tflop number hyped a while back.

Question, but was the TFlop number ever in official press BEFORE the Broadband Engine patent circulated the net? I've only ever known the TFlop projections from that patent myself, but granted I tend to ignore PR when it talks actual numbers.
And obviously the numbers derived from the patent were mainly hyped by this very forum (and the rest of the internet press), never Sony or IBM themselves.

 

[V3]

The streaming processors, described in another paper, are self-contained SIMD units that operate autonomously once they are launched.

So they opted for stream processors afterall ?

So Cell is pretty much like taking out the programmable parts of the typical current GPU, which are stream processors, and putting it on the CPU with the benefit of fine tuning the transistors, to be able to achieve high clock speed.

 

[V3]

Same, I'd like to see how far we (or I) was with: On the Feasibility of the Broadband Engine So far it looks excellent from that article, SRAM @ 4.8GHz, 128KB LS and 128*128bit registers per APU, with 4 FPU & 4 FXU's per APU, upto 8 S|APUs per PE, 6.4GHz RaZor interconnections (with and concurrency will be interesting). Looks to be DMAC heavy to arbitrate, which a few of us have emphasised.

Patent personified so far.

Yeah, its very similar so far, hope we will get more detail soon enough.

 

[V3]

Question, but was the TFlop number ever in official press BEFORE the Broadband Engine patent circulated the net? I've only ever known the TFlop projections from that patent myself, but granted I tend to ignore PR when it talks actual numbers.
And obviously the numbers derived from the patent were mainly hyped by this very forum (and the rest of the internet press), never Sony or IBM themselves.

From Kutaragi, himself, if I remember correctly.

Reading at what EEtimes has reported, 1 TFLOPS using 4 PEs shouldn't be a problem, it seems.

 

[j^aws]

The processing element's DMA controller is so designed, it appears, that any chip in a system can access any bank of DRAM in the cell through a band-switching arrangement. This would make all the processing resources appear to be a single pool under control of the system software.

High level abstraction and software scheduling/resourcing via CELL OS?

 

[Qroach]

Faf,

Question, but was the TFlop number ever in official press BEFORE the Broadband Engine patent circulated the net? I've only ever known the TFlop projections from that patent myself, but granted I tend to ignore PR when it talks actual numbers.

I thought that number came from a sony employee in an interview somewhere?


Vince,

How funny, Look at the difference between what i was going to post and Q did

Wow we found different parts of the article to find interet in

Also, I wouldn't put much faith in Mr. Zimmon's comments, he's doing the same bandwith/flop math that Deadmeat used a year or so ago. External bandwith isn't an indication of calulation ability (ala contemporary GPUs).

Is zimmon's talking about on chip or off chip memory speed?

 

[j^aws]

Seems to be no mention of eDRAM yet? Would we expect it on one PE?

 

[Vince]

Wow we found different parts of the article to find interet in

Exactly, but what was funny is that your selection could have fooled most of us for Deadmeat. You picked out a comment from a PhD from UNC-Chapel Hill that used the exact same, falty, logic that Deadmeat did and we've covered here several times.

And he's talking about off-chip. On-die bandwith will be enormous if the SRAM is running at 4.8GHz and follows the patent. Seriously, haven't you seen his PDF? it's been around for a bit. That's likely why he was asked, not that it's something many on this board couldn't have made.

 

[V3]

Is zimmon's talking about on chip or off chip memory speed?

Come on Qroach.

"The PS3 memory is rumored to be able to transfer around 100 Gbytes/second, which would mean it could process new data at roughly 25 Gflops (at 32 bits) — far from the 1-Tflops number." - Zimmons, UNC

That's the rumoured about the PS3 off chip memory, which is rumoured to be those high frequency Rambus memory. Well not really rumoured anymore since Rambus made a statement about PS3 using them. Its just the configuration is unclear.

 

[one]

Anyway, the actual clock speed of EE was upped 50Mhz from the paper at ISSCC 1999, so similar change (1st gen Cell for workstation, 2nd gen 65nm Cell for PS3) is expected.

 

[V3]

Seems to be no mention of eDRAM yet? Would we expect it on one PE?

Well the patent didn't mentioned about eDRAM either. Most just assume its eDRAM. But there should be a pool of memory, where it can be partition, even for just one PE.

 

[one]

Is zimmon's talking about on chip or off chip memory speed?

Ask him

 

[Qroach]

Exactly, but what was funny is that you're selection could have fooled most of us for Deadmeat. You picked out a comment from a PhD from UNC-Chapel Hill that used the exact same, falty, logic that Deadmeat did and we've covered here several times.

It's not a funny selection, don't be so defensive. Regardless of what the article said, I've always been curious how close they would get to the 1 Tflop number, as numbers like that usually have a way of come out less then promised.

And he's talking about off-chip, seriously, haven't you seen his PDF? it's been around for a bit. That's likely why he was asked, not that it's something many on this board couldn't have made.

Nope. I've stayed clear of all the patent anylayzing and would rather get the real information from sony, if they are indeed talking. I thought this article would have more quotes from sony directly.

 

[j^aws]

I thought this article would have more quotes from sony directly.

I think the ISSCC is still in progress, expect some official press releases after...

 

[V3]

I thought this article would have more quotes from sony directly.

They've got the info from the ISSCC 2005 papers. The conference won't be on for a couple more months, I belive.