Could the RSX be more powerful than originally thought?

[Tacitblue]

Hey guys what is the advantage for Sony to go with a 65nm tech with the RSX and CELL in the future? What would it do, make the machine smaller?

Yeah. PSThree 8)

I don't know if they could do a Dragon Mark II with Cell and RSX, shrinking it down to 65nm would really reduce pad size, there's a HELL of a lot of contacts on each chip, removing FlexIO from the mix is one thing, but you've got XDR on one side, and the soutbridge off Cell and the GDDR3 inferface off RSX. Going to be a bugger to manage it.

 

[Carl B]

Hey guys what is the advantage for Sony to go with a 65nm tech with the RSX and CELL in the future? What would it do, make the machine smaller?

Yeah. PSThree 8)

I don't know if they could do a Dragon Mark II with Cell and RSX, shrinking it down to 65nm would really reduce pad size, there's a HELL of a lot of contacts on each chip, removing FlexIO from the mix is one thing, but you've got XDR on one side, and the soutbridge off Cell and the GDDR3 inferface off RSX. Going to be a bugger to manage it.

Not on 65nm, that's for sure - but maybe at 32nm or something; we should be hitting 32nm at around the same time they like to create their slimmer console versions anyway, so it works out.

(The I/O interface could be problematic though like you said. I wonder if by that time they may have changed the means of contact and interface - as it seems the whole industry will be facing this issue soon)

 

[jvd]

mabye 45nm it will be small enough to put in a smaller case . Though i don't know .

 

[Carl B]

Actually I'm very curious now - is there a successor to pins and/or BGA out there on the horizon?

 

[Tacitblue]

Intel is working on bumpless build up layer tech, but has delayed it until they get the bugs out.

http://www.intel.com/pressroom/archive/backgrnd/20011008tech_bkgrd.htm

http://www.sigrity.com/papers/asme_bbul.pdf

 

[Oda]

Is XboxThreeSixty a possibility for MS, or not because they don't manufacture their own chips like Sony does?

If it isn't, is the only reduction in costs in the 360 over the original Xbox this stuff that MS has done now (own the rights to the IPs I think right)? Can they ever reduce their costs of production down the line beyond the normal depreciation of the system's inards?

 

[Tacitblue]

Is XboxThreeSixty a possibility for MS, or not because they don't manufacture their own chips like Sony does?

If it isn't, is the only reduction in costs in the 360 over the original Xbox this stuff that MS has done now (own the rights to the IPs I think right)? Can they ever reduce their costs of production down the line beyond the normal depreciation of the system's inards?

J Allard and others have mentioned pointedly that there will be consolidation of components in later builds as process shrinks are available.

 

[Carl B]

Intel is working on bumpless build up layer tech, but has delayed it until they get the bugs out.

http://www.intel.com/pressroom/archive/backgrnd/20011008tech_bkgrd.htm

http://www.sigrity.com/papers/asme_bbul.pdf

Good call Tacit, I'd forgotten about that. And while we're discussing future tech, I wonder if a couple of years from now we might not be seeing some processors begin to emerge with that HP cross-bar tech rather than traditional transistors.

 

[aaronspink]

Rumors nothing! If you do the math for the transistor count that should be on the G70 at 110nm with 334mm^2 - we're seriously missing on the order of ~51 million transistors right now.

My rough calcs show that G70 with that die size should be around ~ 360 millon transistors not ~ 300 mil...

But G70 and RSX are on different fabs and for different markets anyway so the tapeouts will be different...

How are you guys calculating these numbers?

You do know that a 130->110 transition has a less relative shrink than 130->90 or 110->90. Generally half steps will be primarily focused on transistor enhancement/shrinking with minor attention paid to the metal stack. In many modern designs it is not uncommon for the metal stack to be the limiter on die size.

Aaron Spink
speaking for myself inc.

 

[cho]

You're saying G70 with 334 mm2 ---> 416 mil trans?

I get 361 mil trans...



NV40

287 mm2 -> 222 mil trannies

If NV40 was scaled to 334mm2 die as G70 but still on 130nm process,

287 mm2 -> 222 mil trannies
334 mm2 -> 258 mil trannies

If that die of 334 mm2 was drooped to 110nm from 130nm but the die size remained at 334 mm2,

(130/110)^2 ~ 1.4x as many tranisitors could be added to the die of 334 mm2.

So,

NV40 scaled to 334 mm2 and dropped to 110 nm,

258 x 1.4 ~ 361 mill trannies

once again, the 287mm^2 for NV40 is a wrong number.

http://www.gzeasy.com/ours/edison/Snap1.png

 

[Carl B]

@aaronspink: Way I was reaching the numbers (similar to how Jaws was doing it I'm sure) was by calculating the increased percentage of transistor density on a process shrink.

1 - ([newer process]^2/[older process]^2) = % gain

I can't address what deviations one process shrink might have against another though; as far as I'm aware the equation traditionally holds up.

BUT...

@cho: Yeah, I think you're right. I was using the die size listed in the 3DTables here at B3D, but after doing a search on the Internet, most sources seem to confirm the higher die area for NV40 given by that picture you linked to.

Which would change things to give NV40 a transistor density of 1,023,041 transistors/mm^2 on a die area of 217mm^2, and assuming a similar density for G70, allow for ~342 million transistors on a die area of 334mm^2. That's still ~40 million 'shadow transistors' that are seemingly missing, but it's less than the 50 and 60 million numbers me and Jaws were talking about.

 

[cho]

The gate density of IBM and TSMC on 130nm for GPUs is different too.

i think the gate density of r420 is lower than nv40 which use IBM 130nm.

 

[aaronspink]

@aaronspink: Way I was reaching the numbers (similar to how Jaws was doing it I'm sure) was by calculating the increased percentage of transistor density on a process shrink.

1 - ([newer process]^2/[older process]^2) = % gain

I can't address what deviations one process shrink might have against another though; as far as I'm aware the equation traditionally holds up.

Past performance is no indication of future gains. For a variety of reasons, most vendors aren't reducing metal sizes as much as they used to. Most of the density improvements are coming from addition additional metal layers and even this is somewhat offset by the need for better power and clock distrobution as voltages decrease and frequencies increase.

In addition, as has been pointed out, this also involves a process vendor transition from IBM which has historically had the most aggresive metal stacks in both number of layers as well as in actual sizing and spacing to TSMC who aren't exactly considered as being aggressive. Cheap, low cost, volume, but not pushing the boundries is the key to TSMC's success.

So if wouldn't supprise me if the metal density has increased minimally (possibly stayed the same) from the 130 nM IBM process to the 110 nM TSMC process.

Aaron Spink
speaking for myself inc.

 

[Geo]

Ironic that someone here links to a story on another site that quite obviously originates from this site!

Wrong tack. Go for "See, other independant observers have come to the same conclusion that I did (first, of course)!".

 

[Wunderchu]

@aaronspink: Way I was reaching the numbers (similar to how Jaws was doing it I'm sure) was by calculating the increased percentage of transistor density on a process shrink.

1 - ([newer process]^2/[older process]^2) = % gain

I can't address what deviations one process shrink might have against another though; as far as I'm aware the equation traditionally holds up.

Past performance is no indication of future gains. For a variety of reasons, most vendors aren't reducing metal sizes as much as they used to. Most of the density improvements are coming from addition additional metal layers and even this is somewhat offset by the need for better power and clock distrobution as voltages decrease and frequencies increase.

In addition, as has been pointed out, this also involves a process vendor transition from IBM which has historically had the most aggresive metal stacks in both number of layers as well as in actual sizing and spacing to TSMC who aren't exactly considered as being aggressive. Cheap, low cost, volume, but not pushing the boundries is the key to TSMC's success.

So if wouldn't supprise me if the metal density has increased minimally (possibly stayed the same) from the 130 nM IBM process to the 110 nM TSMC process.

Aaron Spink
speaking for myself inc.

hmm.. interesting, thanx for the info., aaronspink

 

[Wunderchu]

a little bit of the differences between G70 & RSX, with respect to the connection with CELL, here: http://www.ga-forum.com/showthread.php?t=56541

 

[jpr27]

I was wondering on the G70 vs RSX comparison that if they are indeed that close architecture wise (as far as we know at this time) then what will that do to NV timeframe of future products?

If I remember correctly when Xbox 1 was first released, the GPU (NV2A?) although similar to the PC GF3 more of a GF4 if memory serves me correctly, was tended to be the most powerful GPU at that point in time. (Although I think the GF4 was release a few months after that thus surpassing it in power.) As it looks now and if the PS3 release date (again as far as we know at this time) are true and the RSX was 24 pipe, wouldnt that mean NV more then likely will already surpass the RSX in power (in the desktop area) by the time the PS3 launches? (Due to reacting to whatever ATI is doing with the 520 and beyond)

I dont think this will be the case but does make me think about the 24 or 32 pipes scenerio. Im leaning towards the 32 pipes scenerio with maybe added shader abilities etc. (who knows what NV has or what Sony wanted extra from the archetecture but something is waiting in the wings IMO ) Just like the Xbox 1 NV will probably give a somewhat similar scenario with the PS3 only to surpass the RSX in a few months. (Although surpassing the G70 and RSX is innevitable anyway )

*I'm talking a straight RSX and G70 comparison (from what we know now) because I do know that Cell processor does have the ability to assist the RSX for certain procedures etc. and gaining more performance in certain instances as developers get more experience with the system.*

P.S. Additional thought (its late sorry for the rambling) Could the RSX with some of the additional transistor counts be for say assisting in using HDR +AA scenerio or would the additional transistors be better used else where?

Thoughts? and Corrections? :?

 

[Farid]

a little bit of the differences between G70 & RSX, with respect to the connection with CELL, here: http://www.ga-forum.com/showthread.php?t=56541

Why did you have to bump this old thread just to post a link to a forum thread with the article nondescript translated.... Here in this very forum:
http://www.beyond3d.com/forum/showthread.php?t=22009

Search function is your friend, Wunderchu!