Cortex-A35 announced

[mczak]

This seems to be an interesting little chip.
Albeit it looks to me from an architectural point of view it's more of an optimized and trimmed down Cortex-A53 rather than an evolution of the Cortex-A7 as ARM tries to sell it.
In fact, I can't really find many differences to the A53 so far - ok max L2 cache has gone down to 1MB from 2MB, and it's supposedly more configurable (though if we see that in smartphones we'd certainly see all the optional blocks anyway), but most of the things claimed as new and improved over A7 are pretty much the same as was claimed for the A53. Certainly though some things have been trimmed down compared to A53 but I don't know where (more limited dual issue? Smaller queue sizes?).

 

[Nebuchadnezzar]

http://www.anandtech.com/show/9769/arm-announces-cortex-a35

The biggest improvements were on the front-end, branch prediction and trimming down of the NEON pipe when compared to the A53. ARM said some things in the branch predictor are even newer than what's in the A72. Unfortunately very concrete details on the front-end are hard to get.

 

[liolio]

Believe it or not I was actually thinking about posting something asking if ARM should push a 64bit /ARM V8 processor more akin to the A7 than to the A53. The A53 is nice but Anandtech analysis have shown that ARM may have gone a bit too far with that one as Moore's law finally broke. They need a lower power core for good mature and cheap 28nm lithography.
A53 is going to shine on finfet process but my belief is that 28 nm /planar/cheap transistors are here to last for a little longer than we expected, in that context the A35 is great new. Next the A17

 

[fehu]

Now I expect a dodecacore A35 from mediatek

 

[liolio]

Now I expect a dodecacore A35 from mediatek

I want a septa-core backed by a penta-core of A...ccidentals

 

[iMacmatician]

Regarding the configurations slide, can the smallest configuration of the A35 also be used in a multi-core cluster?

 

[mczak]

Regarding the configurations slide, can the smallest configuration of the A35 also be used in a multi-core cluster?

Can't see why not. At least for A53, I think this was possible in theory with a configuration without L2 and the rest. (And I have to correct myself, it doesn't actually even look like the A35 is more configurable than A53, since all the stuff mentioned as configurable for A35 was so for A53 as well according to arm docs - neon, crypto, l2, acp. Albeit the features were not quite independently configurable for the A53 - acp requires l2, crypto requires neon, fpu requires neon. The marketing material here for A35 isn't specific enough it seems to see if that's still the case.)
And that >10x size difference for smallest to largest configuration looks underestimated to me - of course in the picture it's actually more like a factor of ~50 . But I'd expect the 1MB L2 alone to be close to 10 times the size of that <0.4mm^2 configuration - add in larger l1, neon and of course 4 instead of 1 core and it looks like it's easily a factor 15?

 

[kalelovil]

And that >10x size difference for smallest to largest configuration looks underestimated to me - of course in the picture it's actually more like a factor of ~50 . But I'd expect the 1MB L2 alone to be close to 10 times the size of that <0.4mm^2 configuration - add in larger l1, neon and of course 4 instead of 1 core and it looks like it's easily a factor 15?

I assume the comparison is of an individual core within the quad-core fully-featured configuration (e.g. the area marked CPU0 on the left), to the smallest possible configuration of a core.

Edit: On second thought that can't be right, since 4mm2 is far too large for even an A53. Oddly, the small writing within the core areas on the left seems to be referring to the A53, 'ca53'. Thus I wouldn't rely on the pictures to be actual A35 representations.

 

[Exophase]

Can't see why not. At least for A53, I think this was possible in theory with a configuration without L2 and the rest. (And I have to correct myself, it doesn't actually even look like the A35 is more configurable than A53, since all the stuff mentioned as configurable for A35 was so for A53 as well according to arm docs - neon, crypto, l2, acp. Albeit the features were not quite independently configurable for the A53 - acp requires l2, crypto requires neon, fpu requires neon. The marketing material here for A35 isn't specific enough it seems to see if that's still the case.)
And that >10x size difference for smallest to largest configuration looks underestimated to me - of course in the picture it's actually more like a factor of ~50 . But I'd expect the 1MB L2 alone to be close to 10 times the size of that <0.4mm^2 configuration - add in larger l1, neon and of course 4 instead of 1 core and it looks like it's easily a factor 15?

A35 does have configurable L1 caches. AFAIK that hasn't been a configurable feature since Cortex-A9.

 

[liolio]

It is not featured on the slides but the new core works with the new "interconnect /fabric" (not sure of the correct wording), the Corelink CCN 504.

 

[mczak]

A35 does have configurable L1 caches. AFAIK that hasn't been a configurable feature since Cortex-A9.

The options for the A53 seem to be exactly the same as for A35: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0500f/BABJGAHE.html

 

[mczak]

I assume the comparison is of an individual core within the quad-core fully-featured configuration (e.g. the area marked CPU0 on the left), to the smallest possible configuration of a core.

Edit: On second thought that can't be right, since 4mm2 is far too large for even an A53. Oddly, the small writing within the core areas on the left seems to be referring to the A53, 'ca53'. Thus I wouldn't rely on the pictures to be actual A35 representations.

anandtech quoted 4.6mm^2 for a quad core cortex-a53 (http://www.anandtech.com/show/8718/the-samsung-galaxy-note-4-exynos-review/4). And the chip in question was with 256kB L2 only, on 20nm no less. But maybe the numbers weren't actually for that chip... In any case, I don't think 4mm^2 for 1MB L2 on 28nm is too far off. (The core of a a53 is slightly larger than that of a a35 but in the same ballpark.)

 

[liolio]

anandtech quoted 4.6mm^2 for a quad core cortex-a53 (http://www.anandtech.com/show/8718/the-samsung-galaxy-note-4-exynos-review/4). And the chip in question was with 256kB L2 only, on 20nm no less. But maybe the numbers weren't actually for that chip... In any case, I don't think 4mm^2 for 1MB L2 on 28nm is too far off. (The core of a a53 is slightly larger than that of a a35 but in the same ballpark.)

Well leaving the L2 cache aside, the A53 is actually significantly larger the A35, ARM slides state that the A35 is 25% smaller than the A35 which means that the A53 is 33% bigger than the A35. OK I'm done toying with percentages

 

[mczak]

Well leaving the L2 cache aside, the A53 is actually significantly larger the A35, ARM slides state that the A35 is 25% smaller than the A35 which means that the A53 is 33% bigger than the A35. OK I'm done toying with percentages

Yeah, that fits "slightly larger" for me . It is unclear to what configurations the 25% figure applies, that is it could well be best case. I would for instance expect the difference to be larger percentage wise if you compare 8kB L1 chips vs. comparing 32kB L1 chips.