First of all, they were not making reference to the Playstation 3 explicitly. They were making reference to an article describing the technology covered in the patent, which happened to have Playstation 3 in the title, because that is how the BBC chose to name the article. That does not prove that it is going to be used in the Playstation 3.
That aside, After reading over that patent, a few things become clearer to me.
First, "Cell" is less of a computer chip, and more of a complete restructuring of the idea of a computer network, including a universal instruction set for all processors in the network. That is, ideally they would like to have every processor in the entire broadband network use the same ISA, instead of having a different one for your main processor, graphics processor, broadband modem, sound processor, etc. Basically, they want to replace Intel architecture, AMD architecture, NVIDIA architecture, ATI architecture, etc. and just have Sony architecture-based processors throughout the entire network system. They see the benefit in having all the instructions being able to be interpreted by all of the processors along the way, in hardware. Instead of breaking your web browser's HTTP request into segments, encapsulating each in a packet, then encapsulating the packet into a frame for transmission over a broadband network, the application would simply send the HTTP request as a "Cell software program", which would be automatically understood in hardware at every level. You would no longer have TCP/IP stacks, or sockets, or ports, or ethernet. Everything would be created, sent, routed, received, and processed in "cells".
Second, they obviously realize their design will never be successful if it's an "all-or-nothing" approach. Therefore, they throw in all these little words like "ideally", "preferably", and "In a preferred embodiment". This gives them some leeway allowing them to use Cell processors in systems that have other processing architectures, and software written for those other architectures, but being transferred by, or to, Cell processors in some way. In other words, the patent covers everything from a network interface card that uses a proprietary data link protocol, to an entire network comprising of different types of cell processors, performing different tasks, but using the same instructions.
Third, some of their "ideal" uses seem a bit silly:
The basic processing module is a processor element (PE). A PE preferably comprises a processing unit (PU), a direct memory access controller (DMAC) and a plurality of attached processing units (APUs). In a preferred embodiment, a PE comprises eight APUs. The PU and the APUs interact with a shared dynamic random access memory (DRAM) preferably having a cross-bar architecture. The PU schedules and orchestrates the processing of data and applications by the APUs. The APUs perform this processing in a parallel and independent manner. The DMAC controls accesses by the PU and the APUs to the data and applications stored in the shared DRAM.
In accordance with this modular structure, the number of PEs employed by a member of the network is based upon the processing power required by that member. For example, a server may employ four PEs, a workstation may employ two PEs and a PDA may employ one PE. The number of APUs of a PE assigned to processing a particular software cell depends upon the complexity and magnitude of the programs and data within the cell.
In a preferred embodiment, a plurality of PEs are associated with a shared DRAM. The DRAM preferably is segregated into a plurality of sections, and each of these sections is segregated into a plurality of memory banks. In a particularly preferred embodiment, the DRAM comprises sixty-four memory banks, and each bank has one megabyte of storage capacity. Each section of the DRAM preferably is controlled by a bank controller, and each DMAC of a PE preferably accesses each bank controller. The DMAC of each PE in this embodiment, therefore, can access any portion of the shared DRAM.
Thus, their preferred design is to have multiple PEs access 64 MB of DRAM. In a server, the ideal number of PEs was 4, which gives a server a total of between 64 and 256 MB of DRAM. Given the fact that they explicitly talk about the PE having it's own crossbar memory controller, and having multiple PEs accessing one DRAM bank, I can hardly imagine the DRAM they refer to as being eDRAM. It sounds to me, then, that this patent filed in 2001 was making reference to a server having a maximum total of 256 MB of DRAM (the preferred case having even less, probably 64 MB), and a workstation having, at most, 128 MB.
Now extend this to the Playstation 3. How much RAM do you think it will have total? If they intend to do anti-aliasing, anisotropic filtering, have extremely high polygon meshes, advanced AI, extensive voice and sound, etc. I can't imagine they would release the system with less than 512 MB of RAM. Yet here they are making explicit reference to workstations with 2 PEs that would ideally only have 64 MB of DRAM total. That seems pretty weak to me.
Finally, they make a nice reference to a graphics workstation:
The chip package of FIG. 8 comprises two PEs 802 and 804 and two VSs 806 and 808. An I/O 810 provides an interface between the chip package and network 104. The output from the chip package is a video signal. This configuration may function as, e.g., a graphics work station.
FIG. 9 illustrates yet another configuration. This configuration contains one-half of the processing power of the configuration illustrated in FIG. 8. Instead of two PEs, one PE 902 is provided, and instead of two VSs, one VS 904 is provided. I/O 906 has one-half the bandwidth of the I/O illustrated in FIG. 8. Such a processor also may function, however, as a graphics work station.
It seems that Figure 8 is the best candidate for an ideal computer game console system built using Cell technology, given the examples provided. Two general-purpose processing PUs, and two visual processing PUs containing pixel engines and image caches in the PE, which connect to the external DRAM via an internal I/O ASIC & DMAC unit, hypothetically with 64 MB of RAM. Doesn't sound like the monster people are envisioning, but this probably isn't the design they are intending to use in the Playstation 3.
After all of that, I'm more inclined to believe Cell will make up a large portion of the Playstation 3, but I'm still not convinced it will be used for the entire system, and there is still no hard evidence that explicitly proves it will be.
( do not led the Broadband Engine terms mislead you... it reminds me of how they were presenting the Emotion Engine before it was fully announced it was going to be included in the PlayStation 2 ).
