Panajev2001a said:The DRAM is IMHO embedded... one of the hints is that I do not really see them having an off-chip bus that is 1,024 bits wide
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Reading this "shared" and how they talk about the DRAM HW enhancement for the HW sandboxes, etc... I cannot but think e-DRAM ( especially with all those "shared DRAM" comments ).
65 nm manufacturing technology should also allow for a transistor' budget which allows for e-DRAM being implemented.
IBM was doing research with e-DRAM and when talking about their BlueGene project they mentioned how one of the revolutions of Cellular Computing was solving the memory speed vs CPU speed bottleneck by integrating e-DRAM, thanks to also its smaller cell size compared to SRAM...
e-DRAM thanks to its huge bandwidth is a good solution to keep processor's performance high if you can afford it ( also I don ot believe that the PEs oherwise take THAT ultra much of transistor logic and that there is space for e-DRAMconsidering the transistor budget for a 65 nm process [IBM had a page with some figures with projections of e-DRAM and other things] )...
Sorry if this post seems to jump from one thing to the other and then back and forth...
Ah, yes, after studying more of the diagrams I would agree that the DRAM being referred to is most likely eDRAM. Figure 8 has no DRAM shown on it, and the description for it erroneously referrs to the PUs as PEs. I also overlooked the DMAC labeled on each PU/VS.
In previous diagrams, the DRAM is shown as existing above the PUs. One would then be led to think that the large box of Figure 8 is representing complete PE, containing two PUs and two VSs, with presumably 64 MB of eDRAM included in the package, and connected to the DMACs of each PU/VS.
If this were the PS3 design, the following observations might be made:
The Video output connects the CRT controllers of the PE to a video output interface, and the I/O chip provides an interface for the PE to the rest of the system and the network. The "external memory" is probably regular SDR or DDR DRAM, connected to the I/O chip for this "graphics" PE, the hard disk controller, and the DVD drive controller (probably using a "northbridge" PE for the latter two, since I doubt they will have cell-based drive controllers by then). The peripheral bus probably leads to the input controller PE, network interface PE, and sound engine PE.
The more I think about it, the more elegant it seems, for an enclosed system at least. I don't ever see it catching on for an entire network (well, I could see it replacing Bluetooth, that's about it).
Even if this is the case, however, we are still left with a few concerns. It is unknown whether or not Sony can make an operating system/programming language/compiler capable of exposing all the potential of the Cell system. Having a single ISA is all well and good, but I personally don't know anyone who programs in assembly, and I can't imagine making a large commercial video game without a good set of software tools to do it with. Sony has been criticized in the past for the difficulty of programming for the Playstation architecture. Cell could be better or worse, and the track record doesn't look good.
The other question, is how good those pixel engines will be. We'll have to see how many shading operations they're capable of per clock, and also what kind of clock speeds the eDRAM will allow the chip to operate at. Once that's known (which won't be for a while, obviously) we'll have a better idea of what a game console powered by Cell might be capable of.
I must say, I am starting to see why NVIDIA is so impressed with their design. Microsoft said "lets take what's available (P3 processor, standard graphics chip, etc.) and make it work". Sony is saying "lets take what will work the best (unified instruction set, high bandwidth), and make it available".
