DarkRage said:Ok, so it looks like all of you believe that this comparison is fair?. That all the compilation options and code have received the same attention?. Even when reading the documents IBM states the needed effort to extract as much performance as possible from the SPEs, but not giving any details on the implementation on the 970, for example.
Well, bogging the article down with implementation details on other processors, when the article is supposed to be about Cell, doesn't make much sense. But it is not strictly as you say - for example in the TnL example they do explicitly say that the G5 implementation was a "best effort".
DarkRage said:For example, anyone have a valid explanation, from an architectural point of view, about why a single SPE is 4 times more efficient with Ray Tracing than a 970+Altivec?
Maybe the memory architecture? I'm not an expert on RT implementations, maybe someone else can comment more fully.
edit - beaten by Zeross.