BEHOLD, A CELL Q&A website!!!!!! (CELL to cost $100?!?!)

That basically means it's for backup just in case one of the other SPEs don't work due to defects/bad yields.

 

Yes, but is there a link where SCE says so. It's just I haven't seen it anywhere.
Why do they then even put the 8th spu in the slides if it's just sitthing there with it's thumb in the butt. Wouldn't it be clearer just leave it out of the schematics completely if it's dead.

:? Wouldn't it need to be working then, if it can be used as a backup?

 

Well it's not a specific SPE. You basically build a CELL with 8 SPEs and if one of them is bad that's ok because you only plan on using 7 of them. If all 8 works then one of them won't be used even though it works. If 2 SPEs are bad then you throw away the chip or sell it for scrap.

 

So the 8th SPE carries some bad mojo and all chips that have it functioning are burned in a secret ritual ?
That's just... madness!!

 

Actually I'm not really sure honestly. If all 8 SPEs work then maybe they can use those in CELL workstations/servers or something.

 

rabidrabbit wrote:

Ken Kuturagi said that and showed that on the E3-SonyPressConference.

 

http://abcnews.go.com/Technology/wireStory?id=829220

New details to be released today in accordance with IBM's desire to open source the Cell architecture.

 

"twisting" his thumbs? Ow... That's such a cruel thing to do to silicon, just because it's not good enough.

 

My opinion is they want to launch some where (japan ) by spring time . Which means they have to use 90nm . 250m transistor chip is a huge chip and at 3.2 ghz will be hard to keep yields up .

So knowing this and knowing that they have the flops advantage which is a big marketing term right now , they figured 3.2ghz with 1x7 and 1 disabled for yields would be more than fast enough and will keep the yields bareable .

Very few companys will have 65nm ready this year and even then it will be intel that is rolling it out iwth a small amount of notebook parts just die shrunk to test the process and they will most likely have a ton of problems just like they did with 90nm .

So sony couldn't wait even if it was march of 2006 when thier 65nm plants came online .. there would be no way to ramp production up and get enough chips for a decent launch for at least 4-5 months

 

It's not that complicated to figure out. There's a certain rate of defects per unit area... since you have a large die, you can have more defects per chip. Any one defect in a component can potentially make that component completely useless or at best, make it incapable of binning at that speed.

There's a certain probability that out of all the dies on one wafer, some will have all 8 SPEs completely workable at 3.2 GHz. There's a yet higher probability that that you'll have at least 7 out 8 SPEs in working order at 3.2 GHz. If that higher probability is high enough, then that's what will be produced.

Typically, if the yield rates are below 50%, the product won't be produced or may be sold as some sort of "ultra xt series 9 Mark IV" type of part. With consoles, since you've got something that sells at such low costs, they might require even higher yield rates to keep costs down (in spite of the fact that consoles are not as high volume as PCs).

 

IMHO, I think that they are going to use it to assume some of the overhead in keeping the other SPUs busy. Originally the PPE was going to do this but perhaps they wanted to free up the PPE for work that would better suited to it as opposed to the SPUs.

[/ guessing]

 

No! It IS for yield. That's what Redundancy means (in this context). One SPU will be reserved for being broken and unable to contribute anything. This is to obtain the yields necessary. ie. In 100 Cell dies printed, a perfect 1:8 Cell might make up 20%, whereas those with 1 defective SPE might make 70%.

Nothing more complicated or exciting than that.

 

I would not bet my life on that. I am sure IBM could find lots of uses for Cells with n number of SPEs. To go out of the way and state that we are going to ship this chip with a single redundant SPE smells fishy to me. It is very convenient to blame it on yields but perhaps the shortfall is clock speed necessitated it.

 

That would make it a yield issue all the same. After all, we are talking about yields @ 3.2 GHz. A defect doesn't necessarily completely invalidate a component so much as it could cause it to fail at higher clock speeds (e.g. some dopant bleeding or something -- this doesn't make the component useless, but it would adversely affect the clock scaling).

 

I should have been more clear. I was/am suggesting that if a 4gHz + clock was targeted and it ships at 3.2gHz then perhaps one of the SPEs was inlisted to help the PPE. If there is anywhere in the design that looks to be the weakest link it is the PPE. It is obvious that allowing for a redundant SPEs would increase yeilds but I think the use of the term reserve rather than discard/ignore should raise some eyebrows.

 

Redundancy = Surplus to requirements. (London-boy, back me up on this )

A redundant SPE is one that is there without being used. A SPE helping with management of the other SPE's is in use - therefore not redundant.

Aircraft have redundant systems. They have three of everything. They use 1, but if it goes wrong, they have another two to fall back on. The presence of a redundant SPE therefore means if one doesn't work, we've another spare to take its place.

 

I can play the semantics games as well as any PR department. My first car (1969 Camero) had 350hp of redundant power (i.e.. unneeded to achieve the speed limit) .

 

For what it's worth, this redundancy design was planned at the very start. The patent/paper for doing this was posted around the same time the first CELL patent was discovered. Search among those crazy paper/patent hunting days in this forum for the reference.

 

I'm not giving up:

To me (remember I know very very little about computer rchitecture or programming) the "reserved for redundancy" on the 8th Cell SPE sounds more like it has reserved function(s) like error correction (would good error correction be even more important in a parallel system like Cell?) and maybe drm.

 

Error Correction? Errors are called bugs. I don't think there is a chip designed to do debugging. That's the responsibility of the programmer and game testers.