In chip lingo, a redesign typically means material changes to the original source code. For RTL, that's your verilog code. For analog blocks, that's low level circuit. If you keep the RTL the same but have to resynthesize, it's not called a redesign. Going from 65nm to 40nm with no RTL changes is not a big deal: you point your synthesis tool to a different library file and off you go. Years ago, I singlehandedly ported a large digital design from 0.25um to 180nm in about a week before sending it off to back end. A pure cost reduction with not a single bit of functional changes. For digital logic, it's sometimes that simple. In this particular case, the fab library had similar PLL's, so it was mostly a matter of search-and-replace the few instances.
But it's different for custom analog blocks: there the characteristics of the process can be so different that you have to make major changes. (For custom digital logic, you also need to make changes, but at least you can keep the functionality identical.)
So it's more accurate to talk about partial redesign.
Now say you want to make your first chip in 40nm. What's going to be more painful? Take an existing digital design and only design new analog cells... or start with a completely new architecture but still design new analog cells?
See? To claim that the port of 40nm was a disaster and therefore a switch was made to a full new digital design is just ridiculous.
