ATI RV740 review/preview

[Arun]

I think it was libraries...

In terms of transistor density? Maybe, as I said though I was thinking more about leakage. Certainly the design process (or rather lack of certain things) can influence that, but I'm skeptical it was the main problem there. My point is R600's delays weren't really caused by the process or libraries AFAIK (unlike R520), I'm just talking about the final product here.

65nm, yep we saw the pain and quite a bit more for NVidia than AMD.

Yeah, and I suspect Qualcomm ramped slightly before ATI in that generation (if only by a few months). This time, it seems to me ATI/NV are definitely ramping before Qualcomm. Also while Qualcomm did tape-out much earlier (sometime in 2H07 I think!), that was 45LP and not 40LP and the process NV/AMD are using must be much more different from 45LP than 65G was from 65LP.

How long before a node is "sufficiently mature"? How long was it before AMD stopped paying per good chip on 55nm? Why would AMD be paying per good chip on 40nm right now?

How would I know?! In fact that "sufficiently mature" part is something I added in an edit because I realized that very early pricing mechanisms probably aren't the same as the ones I heard a bit about over the years.

What does AMD's and NVidia's involvement in getting a node up to speed buy them?

I would *guess* prefential pricing, not so much that their pricing is artificially low but that other companies would have artificially high pricing initially so that they don't try ramping too soon. TSMC can't add capacity at light speed (same applies to 55nm BTW, which couldn't have supported NV/AMD at the same time in the early months anyway) and having to buy new tools too fast definitely costs more than buying them later. However, once again I'll admit I don't really know about the specifics here and I'm just speculating...

 

[Jawed]

Oops, that should have been "Why wouldn't AMD be paying per good chip on 40nm right now?"

Jawed

 

[rjc]

Oops, that should have been "Why wouldn't AMD be paying per good chip on 40nm right now?"

I would find that very hard to believe.

Firstly look at the risks - paying per good chip would encourage amd to save costs taking shortcuts in their design as the foundry will pick up the bill for any mistakes made(for example TSMC is not picking up the bill for the nvidia mobile chip problems). Because the world only needs so many graphic chips and TSMC is making all of amd's anyway if they encourage them at 40nm at higher expense too much they will risk losing sales and thus have to depreciate more rapidly their existing 55nm and older equipment(depreciation is 50% of foundry costs)

Secondly look at the money invested in building the chip: AMD has invested in the design and early samples + associated testing. TSMC has researched the node, bought the equipment and set up the production line.

Guessing at costs...say for the first 40nm gpu AMD needed 500 engineers for a year at $100k each = $50million. From here maybe can see cost to the foundry costs would be at least 10x that.

Maybe can see more where the pricing power lies now? The cost of new nodes is ever increasing, shifting control to the foundries, design houses face a much less profitable future than in the past. They will need a regular supply of new unique IP to stay ahead.

Previously in the industry forum i linked a general article to the economist here explaining where things were going. Nobody seemed to notice it much though

 

[trinibwoy]

Maybe can see more where the pricing power lies now? The cost of new nodes is ever increasing, shifting control to the foundries, design houses face a much less profitable future than in the past. They will need a regular supply of new unique IP to stay ahead.

Nice article. Thanks for the link!

I don't see foundries gaining more leverage in the future though. It's the development houses who are pushing the envelope with their designs. Without them the foundries would have no customers for their bleeding edge fab processes. So why would foundries gain a pricing advantage simply because fixed costs are rising?

 

[rjc]

I don't see foundries gaining more leverage in the future though. It's the development houses who are pushing the envelope with their designs. Without them the foundries would have no customers for their bleeding edge fab processes. So why would foundries gain a pricing advantage simply because fixed costs are rising?

Playing devils advocate - how much of this envelope pushing is simply taking advantage of what the new node is providing and how much intrinsic to the design?

What is the last commodity node, that pretty any foundry could provide, say 130nm or 90nm? How would a gpu company compete with 40nm parts from a competitor if they were restricted to either of those older nodes?

 

[silent_guy]

Firstly look at the risks - paying per good chip would encourage amd to save costs taking shortcuts in their design as the foundry will pick up the bill for any mistakes made(for example TSMC is not picking up the bill for the nvidia mobile chip problems).

You don't make shortcuts in a design to compromise yield. It's in nobody's interests, because the interactions between the fab and design houses aren't as black and white as people here seem to think they are.

I don't know about the business side of things, but when yields are low, both sides jump on it to try to find the root of the problem. It's usually not that hard who's at fault (and more often than not, it's not the fab.)

When the fab can prove that a design mistake is the reason for low yields, it's going to be very hard for the design house to make the fab pay for them (and vice versa.) Similarly, no design house is going to foot the bill if the defect density is way lower than expected.

It may seem like it's in either party's best interested to blame the other side, but even more so, it's in both party's interest to solve the problem as quickly as possible, so these kind of joint investigations are usually done in close collaboration.

(BTW, TSMC is in the business of producing raw silicion. Packaging is not what they do, except from smaller scale operations.)

Because the world only needs so many graphic chips and TSMC is making all of amd's anyway if they encourage them at 40nm at higher expense too much they will risk losing sales and thus have to depreciate more rapidly their existing 55nm and older equipment(depreciation is 50% of foundry costs)

On the contrary: since newer nodes are always more costly than the previous one, it makes more sense to shift as much volume to the newer process to make earn back the investments quicker, especially since it gives an edge over the competition.

Maybe can see more where the pricing power lies now? The cost of new nodes is ever increasing, shifting control to the foundries, design houses face a much less profitable future than in the past. They will need a regular supply of new unique IP to stay ahead.

I don't see how fabs are gaining the upper hand. They can only produce what's been thrown in their lap. One competitor is sufficient to make them stay on their toes. The fixed costs of a fab are way higher than those of a fabless house. A fab can't afford to piss off its customers and risk parts of a $10B investment sit idle.

 

[Jawed]

When a design company pays for chips they're paying for chips that have passed as being below a certain defect count, presumably?

The design company then bins for speed (and maybe another threshold of defect testing). So it seems to me yield is a two-part deal:

1. Fab Yield = Chips - defect threshold failures
2. Design Yield = Chips - defect threshold failures - clock target failures ( - on-die redundancy failures)

The design company pays for all chips that the fab doesn't throw away due to defectThresholdFailures. e.g. a wafer produces 400 chips. 40 chips exceed the defect threshold. Out of the remaining 360 chips, 120 can achieve the grade-A clock target and 200 can achieve the grade-B clock target. The remaining 40 chips are junk - perhaps they'll invent a SKU for them down the road?

So the design company has paid for 360 chips, out of which 320 can go into SKUs.

Is that how it works?

Presumably the design company chooses an appropriate degree of wafer-testing probes/techniques to apply to each design. I suppose that implies that the contract with the fab is based upon the extent of defect testing. e.g. the more stringent the testing the higher the price per good chip.

This is interesting about wafer level testing, though quite old:

http://www-ppd.fnal.gov/EEDOffice-W/ASIC_Development/Assets/Presentations/FEE_yarema.pdf

Guaranteed 5% yield at the end

Jawed

 

[trinibwoy]

What is the last commodity node, that pretty any foundry could provide, say 130nm or 90nm? How would a gpu company compete with 40nm parts from a competitor if they were restricted to either of those older nodes?

Yeah but now you're creating an artificial scenario where one customer is willing to pay the inflated prices and that no other fab is fighting for that business. Look at Intel's comment about volumes skyrocketing once fabs move to 450mm wafers. All it takes is one other fab to provide competition and customers will still enjoy significant leverage. Globalfoundries just joined the fray so it's doubtful that foundries will soon hold more sway than they do today.

 

[silent_guy]

Is that how it works?

I really don't know how these are negotiated, but it is definitely not true that a design house will trade-off on test program quality for yield reasons.

That's because yield is way too coarse to measure testing quality. The prime goal of testing is not to zoom in on a yield number plus or minus 1%, it's to reduce the chance of a bad die entering the good die bin down to do a number that's measured in hunderds of ppm. In the big iron telecom world, anything higher than 100ppm is considered unacceptable. The number is certainly higher in a fast moving consumer market (because high 9 reliability is not that important), but it's definitely not going to be 10000ppm/1%. (I'm guessing 500ppm is probably borderline acceptable?)

1% more or less good dies is a relatively minor difference in revenue for the fab, but it get amplified by one or two orders of magnitude for the design house, depending on how long it takes further down the pipeline before the defect is detected.

A more important testing tradeoff is being made wrt tester time. When going from 500ppm to 100ppm, you quickly enter the laws of diminishing returns.

But in terms of fab yield, the difference is in the noise.

 

[rjc]

You don't make shortcuts in a design to compromise yield. It's in nobody's interests, because the interactions between the fab and design houses aren't as black and white as people here seem to think they are.

i was just trying to point out Jawed's idea about good chip pricing was flawed, as it creates opposing motivations between the 2 parties. The pricing has to be set so that it maximises value for both sides. Using "good chip" would create a moral hazard for the design company.

It may seem like it's in either party's best interested to blame the other side, but even more so, it's in both party's interest to solve the problem as quickly as possible, so these kind of joint investigations are usually done in close collaboration.

Contract renewal is the time (privately) for blame. i think from what can work out is ATIs problem at 40nm is that they have been producing the RV740 since the start of the year and the yield has not ramped up as much as they would have expected by now. It started low, but they were hoping it would have improved by today more than it has. From the sound of it they have been making they cannot get enough volume and thus hit their price point below the RV770. The 2 chips are interfering with each other. Similarly Altera seems to be having problems getting volumes of their high end stratix 4 out. Noticed when they announced the mid range arria 2 recently will only be delivering samples this year with volumes not until 2010.

(BTW, TSMC is in the business of producing raw silicion. Packaging is not what they do, except from smaller scale operations.)

Yeah sorry shouldn't included that without a caveat, the same thing is true for the packaging company though they would price on a per chip processed basis and a certain fixed fault level not on a good chip result as like the foundry too much is outside their control. So it wont affect their main business TSMC made announcements last year they were moving more into packaging and testing for advanced nodes here and here

On the contrary: since newer nodes are always more costly than the previous one, it makes more sense to shift as much volume to the newer process to make earn back the investments quicker, especially since it gives an edge over the competition.

Ack no! Not when you're competing with yourself. From link previously gave, foundry costs are: machine depreciation 50%, materials 20%, labor 10%, water and power 5%. By pushing everyone onto your advanced node you are increasing your equipment outlay and depreciation on your older equipment a double hit on your greatest expense.

Where is the competition on the 55nm half node? The aggressive announcements they make future nodes ie 28nm next year is just to initimidate their competition into even trying.

I don't see how fabs are gaining the upper hand. They can only produce what's been thrown in their lap. One competitor is sufficient to make them stay on their toes. The fixed costs of a fab are way higher than those of a fabless house. A fab can't afford to piss off its customers and risk parts of a $10B investment sit idle.

Don't think of demand as a one way street, in black and white so to speak The fabs can increase demand by providing more and more resources(ie design libraries, packaging and testing services) so that setting up a design house becomes easier and easier. From the fabs point of view they want there to be a large quantity of design houses that compete among themselves in effect commoditising the value the designs.

They can do this because the number of people now that can afford to build new fabs can be counted on one hand.

 

[silent_guy]

Using "good chip" would create a moral hazard for the design company.

Just as fixed cost per wafer would create a moral hazard for the fab.
If there's any time in the lifetime of a process to use good chip pricing, it's exactly during the early immature stages.

But, again, I've never had any knowledge about the main price structuring between fab and design house, let alone the footnotes... (And I don't have the Arun's encyclopedic backing wrt chip or company specifics either. Who knows where he got the info about who ATI pays for its silicon? )

... the same thing is true for the packaging company though they would price on a per chip/wafer processed basis and a certain fixed fault level not on a good chip result as like the foundry too much is outside their control.

No, it's not really the same story: I don't know how those deals are structured either, but since the packaging yield is very, very high, it doesn't matter anyway. Long term reliability is different story, but you can't test that during production anyway, so it's impractical to treat it as production yield.

So it wont affect their main business TSMC made announcements last year they were moving more into packaging and testing for advanced nodes...

Sure, but for the reason given above, it doesn't matter anyway. Irrespective of who does what, raw silicon production will always be treated separated from packaging.

Ack no! Not when you're competing with yourself. ...

I'm not convinced, but it's not exactly my cup of tea, so who knows. Same thing about further points you're making.

But as for the point below:

The fabs can increase demand by providing more and more resources(ie design libraries, packaging and testing services) so that setting up a design house becomes easier and easier.

Unfortunately, there's very little a fab can do on this front, because the points you're listing are not where the problem is. Design libraries are already provided by the fab or some vendor. Packaging and testing require some very specialized expertise, but even in larger companies you don't need many of those to make it work (and if you're a smaller company, it's something that can easily be subcontracted to an external expert.)

The lack of new design houses is because of the vast amount of up-front capital that's required to fund front-end design and the lack of truly new fields of technology where the big guys already haven't claimed their stake... A fab could become an active investor in startups themselve, but they won't. Why would they be better than VC's, who haven't seen great returns in the last 5 years.

 

[rjc]

Yeah but now you're creating an artificial scenario where one customer is willing to pay the inflated prices and that no other fab is fighting for that business.

The point i was trying to make is that the gpu design firms dont really have that much choice with regards to the nodes they use. The chips they design are so large will only fit newest nodes. Given that they dont have much choice and the suppliers at the moment appear limited to 1(maybe 2 if include UMC), getting a good deal is going to be very hard.

Look at Intel's comment about volumes skyrocketing once fabs move to 450mm wafers. All it takes is one other fab to provide competition and customers will still enjoy significant leverage. Globalfoundries just joined the fray so it's doubtful that foundries will soon hold more sway than they do today.

Intels comment was that at 22nm or 11nm the typical CPU is probably going to come in below 100mm2....on a 450nm wafer would be capable of 1500 chips compare to today a 300mm wafer at 250mm2 gives 250 potential chips....implies they will need only 1/6 of the wafers they need today. Therefore instead of 10 fabs only need 1 or 2 to supply the world. Obviously these new generation fabs are going many times more expensive than the fabs built today. Today's fabs can only built by a few implying tomorrows will be even more concentrated.

Global Foundries am not really sure yet...i saw a $6billion investment announced for their new fab recently.

 

[aaronspink]

i was just trying to point out Jawed's idea about good chip pricing was flawed, as it creates opposing motivations between the 2 parties. The pricing has to be set so that it maximises value for both sides. Using "good chip" would create a moral hazard for the design company.

Good die pricing is generally only available when the fab is doing the back end of the design. In which case, the fab/foundry is the one responsible for the layout, timing, and design checks. In such a case, the fab can model exactly what is going on and project a relative yield and therefore pricing.

 

[CJ]

"Khan died a few days .... ah serious leakage, a family feels that the only hearsay under casual"
(RV870 or GT215 or GT300???)

Khan... that was good old R300's codename.

 

[trinibwoy]

For real? Lol, now that tidbit means even less sense....

 

[rjc]

Khan... that was good old R300's codename.

Well the full original quote in chinese was: 汗死 前几天啊....漏电严重,某家都不好意思说了只能小道消息散下

something quickly died, leakage, embarassment...my confidence in translation is gone...kindof sad cause the stuff he was saying kindof looked fun to try and decode.

 

[Jawed]

HD4730 is RV770LE

http://www.fudzilla.com/content/view/13916/1/

Jawed

 

[trinibwoy]

Well the full original quote in chinese was: 汗死 前几天啊....漏电严重,某家都不好意思说了只能小道消息散下

something quickly died, leakage, embarassment...my confidence in translation is gone...kindof sad cause the stuff he was saying kindof looked fun to try and decode.

Heh, how come we can never get a perfect translation of chinese forum posts? Do those guys speak some sort of hardcore slang that bilingual folks don't fully understand? A friend of mine who was born and raised in China doesn't even get half the stuff they're saying.

 

[swaaye]

I think I'm most interesting in seeing some notebooks with this GPU. Apparently it's to be used as the Mobility 4830/4860. Can't find any notebooks using it yet though....

 

[rjc]

Heh, how come we can never get a perfect translation of chinese forum posts? Do those guys speak some sort of hardcore slang that bilingual folks don't fully understand? A friend of mine who was born and raised in China doesn't even get half the stuff they're saying.

The language is tonal and has a lot of homonyms(words that sound and spelled the same but mean different things). Also consisted of many amalgamated dialects, language was never really unified(although lots of people have tried).

Most other languages are alphabetic when written(based on sounds, ie all western, some asian like korean and vietnamese were converted from tonal to alphabetic). There is constant raging debate whether this should occur for chinese...would it be impossible and the loss of the artistry currently present in chinese script.

Re sentence. Have been looking more closely. Best i can translate is:
Khan to die...a few days before surprised, leakage critical, family all embarrassed, understand no other choice small path now, news is slowly coming out.

From what i know above could easily be about GT215, although chip would not normally be described as "Khan: Mongol Overlord". The only other candidates are RV870 and GT300 which fit the description. The rest of leak is obviously the chip was too big and could not be made, the only way forward is with small chips.

Edit
According to these guys, AMD have only produced around 40k 4770s so far. Way back in this thread guessed they would want at least 200k to launch...was obviously way too optimistic with that prediction.