Apple Cyclone / A7 Discussion

[Raqia]

There's some nice analysis of Apple's Cyclone CPU in anandtech's iPad Air review:

http://anandtech.com/show/7460/apple-ipad-air-review/2

As far as I can tell, peak issue width of Cyclone is 6 instructions. That’s at least 2x the width of Swift and Krait, and at best more than 3x the width depending on instruction mix. Limitations on co-issuing FP and integer math have also been lifted as you can run up to four integer adds and two FP adds in parallel. You can also perform up to two loads or stores per clock.

Pretty damned wide CPU. Memory interface width is 64 bit now but bandwidth is actually better.

 

[Pressure]

Already discussing it in the Next-Gen iPhone & iPhone Nano Speculation thread.

 

[hkultala]

Already discussing it in the Next-Gen iPhone & iPhone Nano Speculation thread.

I did not find any discussion about it there, only some random post about the 4 MiB cache.

That thread is way too cluttered with other things and finding relevant posts too difficult so lets discuss the cpu architecture here.

 

[Raqia]

Other tidbits include:

-Resizable ROB with iPad air able to have 20% more instructions in flight.
-Low clock speed @1.4 ghz or so compared to Krait 330 @ 2.3 ghz but very high IPC apparent from benchmarks.

At a high level we’re still talking about two 64-bit Apple Cyclone cores with 128KB L1s (64KB I$ + 64KB D$) per core, a shared 1MB L2 cache and a 4MB L3 cache that services the entire SoC. Apple increased CPU frequency from 1.3GHz to 1.4GHz in the iPad Air, a mild increase but in line with what we’ve seen from previous iPad designs. That’s the first impact on performance - a 7.69% increase in CPU frequency.

Looks like a "module" is structured around a pair of cores tied to 1 mb of cache. This might only be for this gen of iPhone though, Apple has the luxury of being able to afford doing a dramatically different microarchitecture each year since they're selling tens of millions of these things.