https://www.anandtech.com/show/1614...en-3-on-nov-5th-19-ipc-claims-best-gaming-cpu
Native 8-core CCX, 32MB L3,
+19% IPC
Too bad consoles missed out on it.
Native 8-core CCX, 32MB L3,
+19% IPC
- +2.7% Cache Prefetching
- +3.3% Execution Engine
- +1.3% Branch Predictor
- +2.7% Micro-op Cache
- +4.6% Front End
- +4.6% Load/Store
As expected in Zen 3, AMD has combined two four core structures (or core complexes, CCX) into a single eight-core structure. This means that all eight cores have access to the 32 MB of L3 cache inside a chiplet, and the latency for each core from 16 MB to 32 MB is greatly improved (previously when you went beyond 16 MB with a core, you would end up in main memory, which is comparatively slower and more power hungry). Due to the increase in L3 cache and the reduced cache latency in this 16-32 MB region, AMD is calling this an ‘effective reduction in memory latency’. No numbers were attached to this claim at this time, and AMD did not state if there were any specific microarchitecture changes in the cache hierarchy to assist with the larger cache access patterns.
But, what we can extrapolate is that whereas in the previous generation, because each chiplet had two core complexes, each complex had its own fabric connection to the rest of the chip. With a single eight-core unified complex design, there is now less core-to-core communication that's required to go off the chiplet. For single chiplet designs, this gets elimated completely, and for dual chiplet designs, each complex only needs to probe one other complex, rather than three. The peak bandwidth should still be the same however, but in a real-world scenario, there should be less cross-talk to deal with. This would scale better for the enterprise hardware, assuming it still retains the eight-chiplet design.
Too bad consoles missed out on it.
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