Wasmachineman_NL
Newcomer
Intel PAT.. god that takes me back.Async clock domains always incur latency penalty during transition. Overclockers will probably try to keep synced IF and DRAM clocks as far as possible, for latency sensitive benchmarks.
Kind of reminds me of the good old i875P chipset for P4, that had special "short path" mode when FSB and DRAM were operating at the same clocks.
@topic: I wonder if Zen/Zen+ will support adjustable IF frequency, would be interesting to see how a 2700X runs on 3200 MHz IF speed.