AMD: Zen 2 (Ryzen/Threadripper 3000?, Epyc 8000?) Speculation, Rumours and Discussion

Discussion in 'PC Industry' started by ToTTenTranz, Oct 8, 2018.

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  1. Rootax

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  2. fellix

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    The memory write throughput is exactly 1/4 of the stated DDR transfer rate, as if somehow the upstream IF bus is clocked at half the downstream rate (or throttled-down at every other cycle). Weird!
     
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  3. Gubbi

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    25.5GB/s is half the DDR4 51.2GB/s theoretical throughput (16bytes/cycle @3200MHz). It appears the upstream IF link is half the width of the downstream one.

    It would be interesting to know where the limitation is:
    1. At the core interface. 25.5GB/s corresponds to just 8 bytes/cycle, unlikely IMO.
    2. At the CCX<->intra-die IF fabric.
    3. At the chiplet interface. 25.5GB corresponds to 32 lanes running at 4x the DDR4 command rate.

    If we could run two copies of the bandwidth test on different cores, and on different cores in different CCXs, we could find out.

    Cheers
     
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  4. Rootax

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    It's a die space saving thing ? Heat/power ? What would you limiting write, but let read speed intact ?
     
  5. Lightman

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    It would be interesting to see how 2 chiplet models behave.
     
  6. fellix

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  7. Rootax

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    Just realized I would need to wait for TR anyway 'cause I need more PCI-E Lanes that x570 is giving us... (I need x16 for my video cards, and x8 for my 10gb nic ... And I don't want to do x8 x8 and limit my vega to x8 speed (even if I probably won't feel the difference, it feels wrong :eek:).

    Well, I'll keep my x99 setup a little more :eek:
     
  8. hoom

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    8* + 8* PCIE4 though, does that not fall-back to 16* + 16* in PCIE3 mode? Or it stays 8* + 8*?
     
  9. Rootax

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    Imo it stays at 8x and 8x. A line is a physical line. Like pcie3 lines didn't double when using pcie2 stuff.
     
  10. tunafish

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    You could in principle put a relay between them that converted the 8x PCIe 4.0 into 16x PCIe 3.0, but you need the extra hardware. (And that would cost some latency, and I don't know if such a bridge even exists yet.) Without it, there's no way for the CPU to magic in the extra physical connections needed by better signaling.
     
  11. rcf

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  12. fellix

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    AMD Ryzen 9 3950X CineBench R15 OC Performance

     
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  13. pharma

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  14. Malo

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    "GameCache"? What are they on about now?
     
  15. AlBran

    AlBran Ferro-Fibrous
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    Their marketing has a bigger budget than.......... well nevermind. :p
     
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  16. hoom

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    Well thats a worry :runaway:
     
  17. hoom

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    To clarify the above since nobody bit: when AMD marketing start making weird bellicose marketing like that its historically a pretty high correlation with a poor performing product.

    Anyway, reading some Anand interviews https://www.anandtech.com/show/14579/all-ryzen-qa-with-amd-ceo-dr-lisa-su
    and https://www.anandtech.com/show/14568/an-interview-with-amds-forrest-norrod-naples-rome-milan-genoa
    some interesting stuff including this pretty amazing point about AM4 socket
    AM4 started with a low-end quad-core Excavator.
     
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  18. fellix

    fellix Hey, You!
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    Socket 7 comes to mind as the most versatile x86 platform and multi-vendor too.
    AMD should know better, since they extended the life of S7 for several years, to support 100MHz FSB.
     
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  19. Rootax

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    I hope they will release some Threadripper news soon... Honestly I don't "want" more than 16 cores, but would like more pcie lines. And I'm curious to see what the "new" memory controller can do with quad channel.
     
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  20. Lightman

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    I'm eyeing 24 core TR Zen 2 upgrade from my 1920X. Hopefully CS GO will finally run well! :p
     
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