Cocktail napkin musing about about the leaked memory bus and speeds, based on the Hynix data sheet.
A 384-bit bus at 6.0 Gbps is 288 GB/s.
A 512-bit bus at 5.0 Gbps is 320 GB/s.
P = f*c*V^2
Since I don't know the capacitance or what other factors might go into calculating the memory bus/controller power.
This makes the (hopefully not too invalid) assumption that those factors are not wildly different.
P = V^2
Bus width*V^2 = an abstracted relative power unit PU
Code:
Width*V^2 PU BW PU/GBs
384*1.5^2 864 288 3
512*1.5^2 1152 384 3
512*1.35^2 933 320 2.92
384*1.6^2 983 336 2.93
512*1.6^2 1311 448 2.93
In this scenario, the density gain for an interface that is close to 2x as area efficient might be more important. The other constraints are a possible absolute power ceiling that makes the 512*6.0 or 7.0options unacceptable, and a refusal to regress in terms of bandwidth.
If we include a factor for clock speed differences, assuming a linear relationship.
P = speed relative to 6.0*PU
Code:
(6/6)*384*1.5^2 864 288 3
(6/6)*512*1.5^2 1152 384 3
(5/6)*512*1.35^2 778 320 2.4
(7/6)*384*1.6^2 1147 336 3.4
(7/6)*512*1.6^2 1529 448 3.4
Not knowing what changes on the GPU side, the area and power savings could be more noticeable if the latter hand-wavy math works out.
Since the rest of the chip is growing in size, any power savings or at power/perf savings would help, even if the peak memory capability is not a big improvement.
I'm curious if the drawbacks are the additional memory device costs and board complexity. Another thing might be the perimeter requirements, which might still be higher even though the overall PHY area is smaller.