What needs to change in the upcoming chip design in order for Tahiti's successor to have an increase in Mtris/sec Setup Rate, an increase in FP16 billinear texel rate, and an increase in Gtexels/sec ROP rate?
edit:
To stay grounded in reality & avoid disappointment, I shall guess that they stayed on 28nm and did a Bonaire-type upgrade to Tahiti resulting in ~30% performance increase.
Contrarily, here is my wishlist for upgrades & improvements:
- More focus on sustainable high clock states via TCP TDP control of voltage regulation
- Some finesse to their Powertune 2.0 C7 voltage/clock states using dedicated circuitry
- A general improvement to maximize "Boost state" performance relative to silicon quality
- Each ASIC sample achieves highest possible mhz depending on leakage (finer grained binning)
- An improved metal bracket (ie EVGA high-air-flow) exhaust from the blower / maximize airflow in shroud
- A redesigned and more efficient Heatsink & cooling solution. (Which I believe has been speculated)
- A "graphics-centric" core design with sacrificed DP throughput (and an alternate ASIC for compute)
- An increase in the number of "ACEs" or setup engines for the 'Front-End'
- A jump to 20nm & 4096+ ALU on a R600-or-greater sized die
- Increased Rasterizer Performance / ROP count & output
- Increase in Mtris/sec, FP16 billinear texel rate, and Gtexels/sec
- Bring back custom downsampling resolutions & scaling in CCC