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AMD: Southern Islands (7*** series) Speculation/ Rumour Thread
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Man from Atlantis
Veteran
what will be AMD's updated 28nm series a.k.a CI(HD8000) bandwidth then?? it seems like we are on the edge with 384 bit w/5.5ghz chips since beyond 6GHz performance degrades, a 448bit or 512bit bus?
One of the things worth watching out for are any reviews that have frame rate graphs or ms per frame recordings.
Some of these changes may not be significant for situations where current cards are at their peak, but may be remedies for known glass jaws that cause ugly performance drops.
The min FPS and latency numbers should be indicative of how much utility AMD can derive from its modifications.
Some of these changes may not be significant for situations where current cards are at their peak, but may be remedies for known glass jaws that cause ugly performance drops.
The min FPS and latency numbers should be indicative of how much utility AMD can derive from its modifications.
Seems like AMD will be using interposers. So the bw is practically unlimited.
This is once in a blue moon transition where math increase is outpaced by mem increase. The trend has been other way round for a very long time.
The roadmap showed GPU+mem interposer at the end of 2013. We can expect they'll release at least 2-3 product generations (or refreshes) in the meantime.
Jawed
Legend
Search for Mintmaster's posts on the topic.
It depends on what you're doing. You can get whatever answer that fits your prejudices. Personally, my prejudices favour bandwidth. As rpg.314 pointed out, ALU FLOP increases typically outpace memory bandwidth improvement which drives benchmarking by marketeers and technology enthusiasts both to focus on largely bandwidth independent code. Again, what are you doing, exactly?
(Effective) bandwidth puts a fundamental limitation on what you can do. It costs money, so you will be supplied with as little as possible, generally.
We can expect a new—but implementing relatively minor changes—generation in late 2012/early 2013, which is likely to stick to the same bus width with a moderate clock bump, and a really new generation in late 2013/early 2014; right on time for interposers, at least according to this roadmap.
After all, Cypress was vastly more powerful than RV770, but both had a 256-bit bus.
itsmydamnation
Veteran
how much more mem throughput will the new cache system buy them vs the old one? will throughput scale with its size? ie if memory speeds hit a wall will cache sizes increases to increase usable memory throughput.
I don't recall clarification on the bandwidth per L2 slice. It was stated as being 64B/clk, but that could mean that it is 64B read+write per clock, as opposed to 64B per clock read-only in previous chips.
For write, that would be a very large improvement over the specialized write path and read-only L2 cache. If it's a static split such that the chip can manage 32B in each direction, then increasing the number of memory channels by 50% and increasing L1 size would be needed to at least partially compensate for a drop in read throughput.
For write, that would be a very large improvement over the specialized write path and read-only L2 cache. If it's a static split such that the chip can manage 32B in each direction, then increasing the number of memory channels by 50% and increasing L1 size would be needed to at least partially compensate for a drop in read throughput.
itsmydamnation
Veteran
isn't that more from a peak perspective? ie could be worse if data is already local/close. what about from an average usage point of view where only some data is local.
AMD's way of enforcing coherency across CU's is to simply kick every modified cacheline after 4 cycles of ALU execution every time.With just a 64B pathway, with all CUs active, it could become a big bottleneck. Unless the crossbar between CU's and L2 was built to service non conflicting transfers in parallel.
Which raises the question, just much more expensive would be such kind of crossbar over a "normal" crossbar? Are these sort of parallel crossbars a common occurrence?
Which raises the question, just much more expensive would be such kind of crossbar over a "normal" crossbar? Are these sort of parallel crossbars a common occurrence?
No cache can help when the locality/reuse is poor.
itsmydamnation
Veteran
but is it really that back and white, ie local caches are big enough to hold all that is needed and you either use a piece of data all the time or almost never?
Not necessarily, the interposer chip presented in the slides could just aswell be just the console -solution, not necessraily related to desktop-parts
The pathological cases obviously can't be helped.
But anything "sane" that uses compute should benefit greatly.
it's not that simple - for example no-one can deny that eDRAM was helpfull and useful for XB360, but you can be sure it's not coming to desktop
Different reasons. Different economics. Bw/pin has stalled on desktop.
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