32 ROPs are surprisingly low. For a 50% bw increase, if they can get ~40% more performance, then I'd say a job very well done.
I'm more disappointed by the lack of Z-rate improvements, given the steady bump in memory throughput.
32 ROPs are surprisingly low. For a 50% bw increase, if they can get ~40% more performance, then I'd say a job very well done.
7950 will have less mem channels then.
43% more transistors than GF110
65% than Cayman
Maybe those transistors went into power saving features and GPGPU features -the caches, EEC, etc.
I am curious if the < 3W idle power means there is power gating involved.
4+1 was a better match to game shaders, since it devoted the +1 to a lot of specialized functionality that either did not get used in scientific computing or lacked the precision to be used for serious computation.
With "only" 65% more transistors than 6970, something like ~50% faster still doesn't sound that great (especially considering Cayman didn't have the best perf/area ratio, still it's not too bad). The speculated die size (similar to Cayman) is indeed rather large though, I might miss some details but theoretically you could fit twice as many transistors on 28nm compared to 40nm within the same area.We should wait until we see the die size and TDP confirmed.
The target die size is lower and the stock power limits probably cap performance in a power-dominated situation.
With "only" 65% more transistors than 6970, something like ~50% faster still doesn't sound that great (especially considering Cayman didn't have the best perf/area ratio, still it's not too bad). The speculated die size (similar to Cayman) is indeed rather large though, I might miss some details but theoretically you could fit twice as many transistors on 28nm compared to 40nm within the same area.
With "only" 65% more transistors than 6970...
With "only" 65% more transistors than 6970, something like ~50% faster still doesn't sound that great (especially considering Cayman didn't have the best perf/area ratio, still it's not too bad). The speculated die size (similar to Cayman) is indeed rather large though, I might miss some details but theoretically you could fit twice as many transistors on 28nm compared to 40nm within the same area.
Do anyone, by any chance, have a pointer to sites with benchmark shmoos for shader and memory clocks? Especially where wide ranges are used, not just minor overclocks.rpg.314 said:The bandwidth is 50% higher, so that's an upper bound right there.