AMD: Southern Islands (7*** series) Speculation/ Rumour Thread

Discussion in 'Architecture and Products' started by UniversalTruth, Dec 17, 2010.

  1. Kaotik

    Kaotik Drunk Member
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    That would be highest res of the Tahiti die I've seen so far?

    Though looks like they did less than perfect job scraping layers :razz:
     
  2. Rangers

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    I wasnt expecting 400 for 7870 rather 349. I was going by this that was posted, seems reasonable: http://www.3dcenter.org/news/die-spezifikationen-zur-amd-radeon-hd-7800-serie

    It lists 349 for 7870 and 279 for 7850.

    Only caveat is I could see 249 instead of 279 for 7850. That would be better.

    Dont really see less than 349 for 7870 based on price/performance and AMD's SI pricing to date. It should be faster than a 6970 that recently retailed for 349 for example.

    Definitely cant see 400 for 7870, that pushes too close to 7950 and leaves no room for future 1.5 GB 7950 that was rumored at 399.

    AMD could also use a card between 7770 and 7850 perhaps methinks. Probably coming later at some point.

    IF they do 299 for 7870 that would be very nice, not expecting it though. It would also leave too big a pricing gap between 7870 and 7950 (299 to 450 with nothing between).
     
  3. Alexko

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  4. Kaotik

    Kaotik Drunk Member
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    7790 or 7830 with further handicapped version of Pitcairn will fill that void for sure
     
  5. Man from Atlantis

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  6. AlphaWolf

    AlphaWolf Specious Misanthrope
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    I'm sure there will also be OC models that will fill gaps in pricing structure. There's also the half memory sku's.
     
  7. jaredpace

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    Yeah here's some more

    [​IMG]

    [​IMG]

    [​IMG]

    [​IMG]

    [​IMG]
    :p
    http://www.chipworks.com/en/technic...e-the-asus-amd-7970-graphics-card-tsmc-28-nm/
     
    #3007 jaredpace, Mar 4, 2012
    Last edited by a moderator: Mar 4, 2012
  8. Alexko

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    For the small, small price of $2,500! :D
     
  9. Gipsel

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    Btw., Chipworks says Tahiti is fabbed in the 28HP process.
     
  10. fellix

    fellix Hey, You!
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    The multiprocessors are obviously grouped in quads -- shared scalar and instruction caches, incl. some logic, are clearly visible between the TMUs and the compute units.
    As an old tradition, the ROPs and memory controllers are placed around the perimeter of the ALU array, while the central "spine" houses the pair of command and primitive setup pipelines. The display logic and all the misc. I/O is at the bottom of the shot.

    The general layout follows pretty similar pattern since RV770. ;)
     
  11. no-X

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    So... hypotetical Tahiti with 256bit bus would be just ~320 mm² large. It seems, that GCN and Kepler will offer pretty similar perf/mm² ratio.
     
  12. Gipsel

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    I doubt a bit that it is between the TMUs and the CUs. There is this typical box of the SIMD engines (where the logic is surrounded by the SRAM arrays for the reg files) on both sides of the shared stuff (which would mean each of these blocks is comprised of two SIMD engines). My guess for the TMUs would be that they are all oriented to the middle of the die, not the edges (and the structures there look a bit like the RV770 TMUs). The center of a CU would be a natural place for the scalar ALU, the LDS and the scheduling stuff in my opinion. Two SIMD engines are then located to either side of that. It appears a bit strange that AMD would also put the shared logic/caches for the CU groups in the middle of the CUs. But who knows? Maybe the close location of the scalar and instruction caches is necessary for the latency they shooted for. I don't know.

    Edit:
    That layout would actually fit with one impression I got from available material regarding the LDS access. The description in the available material supports the idea of two independent data busses connecting the LDS to the SIMD engines, one for SIMD 0 and 1, the other for SIMD 2 and 3. Also something that will work best, if the LDS is in the middle between the SIMD engines.
     
    #3012 Gipsel, Mar 4, 2012
    Last edited by a moderator: Mar 4, 2012
  13. fellix

    fellix Hey, You!
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    My attempt to "enhance" the die shot... sorry, don't have $2K for the RAW shot. :p

    [​IMG]
     
  14. 3dilettante

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    I'm not several thousand dollars worth of curious about the chip to know more of the gritty details.

    The pic's size of 600x535 pixels, if applied to a 365mm2 chip, gives roughly 880 pixels per mm2.
    Each CU would then be between 6 and 7 mm2, maybe under 6.5.

    In terms of CU area, almost half the die is in those arrays.
    The costs of high speed PHY are pretty steep, with 20% of the die just for the memory interface.
    That leaves about a third of the die for everything else.
     
  15. AlNets

    AlNets ¯\_(ツ)_/¯
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    Someone wanna draw coloured box outlines for what's what? :p
     
  16. fellix

    fellix Hey, You!
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    Yep, the CU array takes exactly half of the chip die area. The ROP partitions are very compact, though. Good scaling there.
     
  17. silent_guy

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    Finally!
    Thanks, Chipworks, I hope this is the beginning of a great tradition!
     
  18. fellix

    fellix Hey, You!
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    [​IMG]
     
    #3018 fellix, Mar 5, 2012
    Last edited by a moderator: Mar 5, 2012
  19. Acert93

    Acert93 Artist formerly known as Acert93
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    Thanks Fellix.
     
  20. AlNets

    AlNets ¯\_(ツ)_/¯
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    Thanks fellix!

    Gosh, that memory controller is fat.
     

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