Intel's optimization document recommends paying attention to the number of independent buffers being written to and trying to segregate different types of write traffic. The software is expected to do what it can to increase the chances that a full run of non-temporal writes will occur before eviction or some other condition for writeback is met. That means trying to avoid regular loads in the middle of filling a buffer, and capping the number of independent buffers being written to in an inner loop. For prior generations, Intel only guaranteed 4 such arrays for simultaneous use. (3.6.10)
If the code is multithreaded, section 8.5.5 includes a recommendation of using a small buffer in writeback memory to coalesce write-combine partial writes into a single final copy to WC memory rather than engaging in a stream of partial writes that might be interrupted. Section 7.7.1 advocates a similar use of small buffers and final full-line WC copies.
The details for write-combining are more sparse as time goes on, but the overall tone is that software is responsible for avoiding problems with partial writes or thrashing.
As to how AMD is different, it's unclear. AMD's older cores had a more detailed list on how they might flush their buffers, whereas Intel does not. The lack of transparency was part of the motivation of some earlier references to those encouraging avoiding write-combining or non-temporal instructions, since the exact behaviors are so variable and not always communicated.
I did see a rather oblique tweet to the effect that maybe some of the uncached operations under discussion for Zen's performance in certain games might not be as uncached as some are assuming, but I did not see additional detail.
