itsmydamnation
Veteran
From AMD stating that the Naples 2p platform only has 64 PCI-E lanes per proc not 128 like the 1p, so each zepplin SOC is using 16 lanes of phy , my assumption is that xGMI will be PCI-E 3.x based in terms of encoding etc ( AMD have said they can do infinty fabric over PCI-E as well) because of distance, i guess it could be 802.3 based but then there wouldn't be any inter proc issues like neilz hinted at.I don't get where this is from?