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iMacmatician
Regular
I don't know if this article has been posted here before (it's from August 2016), but I recently saw it linked on the Real World Tech forum.
"AMD Finds Zen in Microarchitecture."
There's a lot of information, including SPECint_rate2006 Base estimates for various CPU cores.
"AMD Finds Zen in Microarchitecture."
There's a lot of information, including SPECint_rate2006 Base estimates for various CPU cores.
David Kanter said:
There are some tidbits in there that would warrant commenting on after I have time to let the information percolate (no stack engine in BD, EX seems to disagree with other sources like Agner's optimization doc, non-inclusive uop cache, etc.), but was libquantum any less broken between AMD and Intel? It might be worthwhile to have an apples to apples comparison if they're equally cheating. Libquantum was actually an area where BD did better, for what that's worth.
itsmydamnation
Veteran
The other things to remember are that:
AMD have stated they beat 40% target IPC increase
Zen appears to be able to clock higher atleast in the 8 core consumer part.
Those 256bit ops blow the TDP out while down clocking so Zen should be able to clock higher, broadwell/skylake a little lower and the gap reduces a bit.
AMD have stated they beat 40% target IPC increase
Zen appears to be able to clock higher atleast in the 8 core consumer part.
Those 256bit ops blow the TDP out while down clocking so Zen should be able to clock higher, broadwell/skylake a little lower and the gap reduces a bit.
I'm unsure how to interpret the Linley article's point about the L1 Icache being physically addressed, and the uop cache potentially also being physically addressed. If both are due to the TLBs being put into the prediction pipeline, and addresses being translated prior to making a cache access, does this negate the L1 Icache aliasing issue that the VIPT cache of earlier generations? Even with the higher associativity of the Zen L1I, it would still have insufficient associativity for its size to avoid the issue if VIPT.
However, is it really a TLB if the address is calculated before hitting the caches (what is the Look-aside function if it was looked at earlier)?
The article indicates the memory file in the front end is related to the stack engine, although AMD's slides seemed to be a little broader in crediting it for load to store forwarding as a separate bullet point.
The article does indicate Zen uses MOESI, which may have some implications since it seems this and other elements like the L3 share some high-level features with the less-impressive L3/LLC cache subsystems of prior generations. Perhaps if there is a directory or filter system in place, the scalability issues for broadcasts and invalidates are less prominent at higher core/chip counts.
The article describes AMD's implementation of FMA as being two FMA units and two FADD units, rather than bridging MUL and ADD pipes. An FMA would steal a read port from an ADD pipe.
This makes sense, although I wonder if that stands for an optimization in the future if the CPU (and its supposed "neural net") could detect a reused or overwritten register and have the FMA pipe satisfy its third operand slot over multiple cycles. Speculatively, might not something like that be done for operands in the integer pipeline? If there were feedback to the decode/uop cache, a loop might even decode into uops that say "reuse this operand", with care taken for any sort of branch/exception recovery to fall back a more conservative checkpoint.
However, is it really a TLB if the address is calculated before hitting the caches (what is the Look-aside function if it was looked at earlier)?
The article indicates the memory file in the front end is related to the stack engine, although AMD's slides seemed to be a little broader in crediting it for load to store forwarding as a separate bullet point.
The article does indicate Zen uses MOESI, which may have some implications since it seems this and other elements like the L3 share some high-level features with the less-impressive L3/LLC cache subsystems of prior generations. Perhaps if there is a directory or filter system in place, the scalability issues for broadcasts and invalidates are less prominent at higher core/chip counts.
The article describes AMD's implementation of FMA as being two FMA units and two FADD units, rather than bridging MUL and ADD pipes. An FMA would steal a read port from an ADD pipe.
This makes sense, although I wonder if that stands for an optimization in the future if the CPU (and its supposed "neural net") could detect a reused or overwritten register and have the FMA pipe satisfy its third operand slot over multiple cycles. Speculatively, might not something like that be done for operands in the integer pipeline? If there were feedback to the decode/uop cache, a loop might even decode into uops that say "reuse this operand", with care taken for any sort of branch/exception recovery to fall back a more conservative checkpoint.
Its the problem with this type of calculation.
they have take quadcore as comparaison point, who ofc for Intel are clocked effectevely rather high ( 6700K@4-4.2ghz ), ( their IPC result is depending on the clockspeed of each model there. )
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Zen core area breakdown:
http://www.eetimes.com/document.asp?piddl_msgid=368302&doc_id=1331317&page_number=2
http://www.eetimes.com/document.asp?piddl_msgid=368302&doc_id=1331317&page_number=2
The L2 number is at the upper limit of the rough guess I got from the leaked die shot earlier in the thread.
https://forum.beyond3d.com/posts/1916209/
The hand-waving and error margin were generous in that post, however.
That would seem to put the Zen core in the 5mm2 range give or take, if the error in core estimate is consistent with that of the L2 calculation.
The size difference for some of the Intel elements does lend credence to there being a cost to the vector units and the plumbing in the cache to handle them. The L3's modularity might have cost some density as well.
https://forum.beyond3d.com/posts/1916209/
The hand-waving and error margin were generous in that post, however.
That would seem to put the Zen core in the 5mm2 range give or take, if the error in core estimate is consistent with that of the L2 calculation.
The size difference for some of the Intel elements does lend credence to there being a cost to the vector units and the plumbing in the cache to handle them. The L3's modularity might have cost some density as well.
If they're being consistent, then I would say yes. The area per core for Skylake is over 12mm2 if it weren't including L3 in the overall figure. It seems closer to what is expected if this is the area of a core+L3 complex.
I read it as larger for Zen: 0,08 mm2 vs 0,058 mm2 ( Intel )
itsmydamnation
Veteran
I think he means given that why is the overall area smaller for Zen.
im guessing throughput, intel cache can move twice the data per cycle , intel needs it because of twice the L/S bandwidth per core because of full rate 256bit ops.
D
Deleted member 2197
Guest
https://world.taobao.com/item/543819565628.htm?fromSite=main
Edit: Yea, they pulled the link ...
http://www.guru3d.com/news-story/am...ces-at-taobao-with-28th-feb-availibility.html
Edit: Yea, they pulled the link ...
http://www.guru3d.com/news-story/am...ces-at-taobao-with-28th-feb-availibility.html
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A link to some sort of preorder form for AMDs Taobao channel, with the interesting bits being date (Feb 28th), price (~300$) and base clock (4.2Ghz).
Here's an article on it: https://www.techpowerup.com/230464/...urfaces-mark-your-calendars-for-february-28th
Well, could just been for traffic on the shop. I dont remember if the price in Yen are slighty lower than other country, but this seems way to low for the 8cores, and we know that quadcore and 6cores should come way later..
This said some samples was allready at 4ghz, why not 4.2ghz TB ( at least for a 6cores ).
This said some samples was allready at 4ghz, why not 4.2ghz TB ( at least for a 6cores ).
Do you have any privilege info to back that up? because AMD said "full family chip available from day one.
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