AMD RyZen CPU Architecture for 2017

[tunafish]

Athlon 64?

Haha no. Missed by 6 months IIRC.

Regardless, it depends on what you mean with "on time".
Zen may be "on time", but it's not like AMD set themselves up for any speed record on putting a new architecture out there.
Zen started its development in 2012.
Between 2012 and late 2016, ARM will have transitioned from Cortex A9 to Cortex A15, then mid-gen transition Cortex A12/A17, then major transition to ARMv8 with Cortex A57, then Cortex A72, then mid-gen transition Cortex A73.. and that's only in the high-end.
Intel did two "Tick-Tocks" and a half, practically 6 different CPU cores from Sandybridge to Kaby Lake.

Considering the rather small upgrades that the Bulldozer family got throughout the years, it's a bit hard to believe their blunt workforce was focused on that architecture.

They took roughly the same amount of time to make a new architecture as Intel and ARM. Intel and ARM release new architectures more often because they both have multiple design teams working on different projects in parallel, and also because they pipeline their teams, having the high-level design team move onto next design as soon as they pass their work for the lower-level teams. AMD does this too, but when you need to do a radical re-design we have to wait for the full 5 years before we see any results.

 

[Blazkowicz]

So there was an annoucement for Bristol Ridge and Stoney Ridge : the CPU provides 4 USB 3.0, 4 USB 2.0 and two SATA 6Gb through its pins. That was an annoucement for laptop chips though, not specifically desktop AM4.

Only 12x PCIe too like current Carrizo.
Will AM4 provide the same USB and SATA then?

It's pretty amazing that so many stuff coexist without being buried in noise and crosstalk, although that's what a SoC is.

 

[hoom]

Yeah I hadn't realised they were going full integrated Southbridge
Would certainly expect a lot more than 12 PCIe lanes for Summit Ridge, these APUs are still 28nm right? -> should be much more room for stuff on 14nm.

 

[Kaotik]

So there was an annoucement for Bristol Ridge and Stoney Ridge : the CPU provides 4 USB 3.0, 4 USB 2.0 and two SATA 6Gb through its pins. That was an annoucement for laptop chips though, not specifically desktop AM4.

Only 12x PCIe too like current Carrizo.
Will AM4 provide the same USB and SATA then?

It's pretty amazing that so many stuff coexist without being buried in noise and crosstalk, although that's what a SoC is.

AM4 won't use the south bridge from the APU (as one doesn't exist in Zen), but it's own south bridge

 

[pTmdfx]

AM4 won't use the south bridge from the APU (as one doesn't exist in Zen), but it's own south bridge

I don't think so. Previously leaks suggest the AM4 socket itself provides a minimum set of I/O, while the likely optional chipset provides an extended set. The essential I/Os like SPI for BIOS is integrated now.

 

[Blazkowicz]

If they go further on the configurable TDP idea and allow to move the CPU from a really poor little MB (no chipset, PCIe 8x and perhaps single channel) to a more full featured one and vice versa, you have some nice versatility there.

Move parts freely around between a tiny, small or special form factor PC and a full ATX tower.

 

[Deleted member 13524]

Rumors saying that today's presentation from AMD at E3 will include showing off Zen playing games.
Heads up.

 

[hoom]

They had footage in the proving lab, including playing Doom, no fps or settings.
Nor any tech details of Zen.

 

[eastmen]

They had footage in the proving lab, including playing Doom, no fps or settings.
Nor any tech details of Zen.

She said 8 cores I think

 

[hoom]

Well she said that at Computex already.

More interesting is that new Xbox is apparently going to be an SoC with 8 core Zen + Polaris

Thats the sort of horsepower I was hoping for in a Zen APU for desktops
I wonder if there would be some kind of exclusivity that would prevent AMD using equivalent setup for PC?

 

[Grall]

The thing which might concern people somewhat is that apparently, zen does not support 256-bit SIMD? That's been in Intel chips since haswell gen.

 

[hoom]

I thought it was going to get the famous bridged 128bit FMAC?

On topic of PCIE lanes: http://www.fudzilla.com/news/processors/40888-amd-naples-zen-has-32-cores says the 32core chip will have 128 PCIE lanes.
I'm thinking if we assume that is made up from essentially 4* the 8core block then the 8core chip should have 32 PCIE lanes

 

[Alexko]

Well she said that at Computex already.

More interesting is that new Xbox is apparently going to be an SoC with 8 core Zen + Polaris

Thats the sort of horsepower I was hoping for in a Zen APU for desktops
I wonder if there would be some kind of exclusivity that would prevent AMD using equivalent setup for PC?

The Xbox One's APU was co-designed by Microsoft, I believe; if that is also true of Scorpio's, the same restrictions would probably apply. Plus it might just not be PC-compatible.

 

[Blazkowicz]

Well she said that at Computex already.

More interesting is that new Xbox is apparently going to be an SoC with 8 core Zen + Polaris

Thats the sort of horsepower I was hoping for in a Zen APU for desktops
I wonder if there would be some kind of exclusivity that would prevent AMD using equivalent setup for PC?

Bandwith obviously. I will sum up how you might do it :
- a socket and motherboard with eight-channel DDR4
- a HBM2 stack fitting next to the APU, on a classical socket
- eight GDDR5(X) chips soldered around the CPU (sixteen in clamshell mode), either on the motherboard (fixed RAM) or on an MXM-like module (buy the whole module if you want 8GB or 16GB RAM)
- eDRAM or ESRAM in the APU and e.g. a quad channel socket and motherboard. (similar to Intel GT3e/GT4e or first Xbox One)
- (cancelled, too few many players in the RAM industry) GDDR5M DIMM/So-DIMM, quad channel if you want it really powerful

Just expensive, and current consoles were unusual with their memory bus width, they ate that cost although having just one big main chip is a saving.

Perhaps in the farther future you'll see some HBM-like for the APU, or HBM plus external DRAM (two memory pools one slow and one fast. one of them optional)
In the near future if you want benefits of an APU (getting rid of PCIe latency) and you don't mind paying like > $1000 there might be something coming on that server socket, which might be physically big enough too (like Pentium Pro)

 

[Blazkowicz]

I thought it was going to get the famous bridged 128bit FMAC?

On topic of PCIE lanes: http://www.fudzilla.com/news/processors/40888-amd-naples-zen-has-32-cores says the 32core chip will have 128 PCIE lanes.
I'm thinking if we assume that is made up from essentially 4* the 8core block then the 8core chip should have 32 PCIE lanes

I remember word that the server CPU is based on a 16-core die (put two of them for a 32-core CPU), there may well be 8-core clusters underneath but I bet they do whatever with the PCIe lanes?

 

[itsmydamnation]

AMD went to the effort of creating a distributed memory architecture ( separate memory controllers/interfaces, separate L3's) is doesn't make much sense for amd to then turn around and make two SOC's for the server market. IMHO the 32 core part will be 4 8core soc's linked together via GMI. the Server APU version will switch 2 of those 8core socs's for one Vega GPU again all connected via GMI.

 

[kalelovil]

AMD went to the effort of creating a distributed memory architecture ( separate memory controllers/interfaces, separate L3's) is doesn't make much sense for amd to then turn around and make two SOC's for the server market. IMHO the 32 core part will be 4 8core soc's linked together via GMI. the Server APU version will switch 2 of those 8core socs's for one Vega GPU again all connected via GMI.

Additional GMI links on each die would be needed to accomplish that, die area which would then be wasted when the same dies are used in single-node applications (Summit Ridge).
Whether that outweighs the cost of a whole new 16 core die or not, I don't know.

 

[itsmydamnation]

not if its a ring it wont. We have already seen via publish patches that the Zen L3 needs to be/is locality aware, its not like intels where the hash that determines the L3 write can select any L3 slice.

 

[Blazkowicz]

I think the AMD strategy of one type of die per CPU just sucked. There were more sockets than dies and sockets have their cost too.
E.g. one FX die for AM3+, C32 and G34 (MCM) ; one APU die for whatever the platform was at a given time, plus AM1.

So if you wanted low end, AMD has only had fat disabled dies for you.

C32 was a big failure, I've never heard of a server using it and workstations went single socket Intel. Could have stuck with a single die for FX and Opteron but skipping the middle socket.
Now AMD has a low end *-Ridge die in the main APU line and they go from five desktop/server sockets (not counting the dead FM1 and the FM2+ half-gen) to two + soldered stuff. That will be saner.
If there is a 16-core server die, they go from three dies to four (dropping Jaguar)

 

[3dilettante]

AMD went to the effort of creating a distributed memory architecture ( separate memory controllers/interfaces, separate L3's) is doesn't make much sense for amd to then turn around and make two SOC's for the server market. IMHO the 32 core part will be 4 8core soc's linked together via GMI. the Server APU version will switch 2 of those 8core socs's for one Vega GPU again all connected via GMI.

How many lanes of IO is the assumption for these dies?
There were two different Zen APU slides that had a Greenland GPU.
One is the one showing an MCM with Zeppelin and a Greenland GPU with 4 GMI links between the GPU and CPU.
The other was an HPC APU with equivalent memory, CPU, GPU, and other features.
The latter gave this APU 64 lanes of PCIe connectivity.

They could be different concepts, although the 32-core rumor and its 128 lanes of PCIe seems to allow for the HPC APU being the same as the other slide and for its CPU component to be Zeppelin.

Is there enough in that "GMI" block in the Summit Ridge photo to give that much connectivity? It doesn't seem like there's another stretch of non-DDR IO that can give enough PCIe lanes, so it would seem like that area has multiple uses.