AMD RyZen CPU Architecture for 2017

I think the launch is expected at the end of this year. So we can expect gradually more detailed teasers leading up to that, starting perhaps toward the end of summer of the beginning of fall. That's more or less how these things usually go.

Just to be clear, the earlier teasers would include almost no actual information.
 
Competitive with skylake, only that this fall it will be replaced by kabylake...

However we won't see 8 core Skylakes until next year in all likelyhood as we haven't even had 8 core Broadwells yet. This is where Intels unfathomable choice to always run the E range of CPU's 1 IP generation behind the mainstream CPU's will hopefully come unstuck. There is a gap there for AMD to exploit and I hope they do it well. If we can get 8 cores of Skylake performance for the same price as 4 cores of Kabylake performance I sure as hell know which one I'd opt for.
 
Competitive with skylake, only that this fall it will be replaced by kabylake...
Kaby will be a handful of percent faster than skylake, no more. Well, excluding graphics, that is. If zen targets skylake-level performance, kaby won't make it instantly obsolete. Intel is merely going through the motions of building new CPUs these days without a real competitor chasing them. Hopefully zen will stir things up. Who knows, maybe I'll even go back to the red team on the CPU side for the first time since the K6-III... ;)
 
Up there with Skylake for power & singlethread while being cheaper? I'll take one for sure.

Had actually been wondering last couple of days why there has been such little news recently.
 
I actually wonder if Kaby Lake will have any IPC improvements on the CPU cores at all.
Most rumors have been pointing to a glorified Skylake refresh with a somewhat better GPU, native USB 3.1 support, HDMI 2.0 / HDCP2.2 and full HEVC 10bit fixed function encoding.
Hopefully, they'll also work on the Connected Standby S0 mode for the Y and U-series, which is basically broken on Skylake.
AFAIK, the single-chip Y/U for mobile chips won't even support LPDDR4, which will have been in use for almost 2 years when Kaby Lake releases.
 
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I hope that graph showing twice the Bulldozer performance is based on 8 core model. Wonder what clock speeds new Zen cores will run at when released. Again hoping for 3GHz to 3.5GHz for big Zen.
This might be AMD's chance to win me back on the CPU side as my last AMD CPU was Thuban (AMD X6 1100T).
 
hope that graph showing twice the Bulldozer performance is based on 8 core model.
Its quite a worry really.
Orochi is the original 32nm Bulldozer 4 Module (8 thread) chip so they damn well better be doing at least 2* the multithread performance with a several generations later, 2 process nodes smaller, true 8 core (16 thread SMT) chip...

my last AMD CPU was Thuban
I'm still on my Thuban, feeling pretty desperately in need of replacement.
 
The Orochi/Zen comparison graph is unitless, unlabeled, may not be normalized, and doesn't align with the Cinebench graph to its left.

If we were to assume that it was the same Cinebench R15 MT benchmark, it would put a presumably 8-core/16-thread Zen in the general vicinity of 6 or 8 core Ivy Bridge chips, at least going from Anandtech's list of Cinebench results. I suspect the graph is as meaningless as it appears, though I can't speak to whether AMD was trying to create an association by proximity.
 
Its quite a worry really.
Orochi is the original 32nm Bulldozer 4 Module (8 thread) chip so they damn well better be doing at least 2* the multithread performance with a several generations later, 2 process nodes smaller, true 8 core (16 thread SMT) chip...

I'm still on my Thuban, feeling pretty desperately in need of replacement.
Remember that Zen is still only 256/128 L/S a core and 128bit SIMD units just like Bulldozer. Big high ILP throughput SIMD style workloads aren't going to see the same level of performance improvement per core as regular branchy lower ILP code.
 
Remember that Zen is still only 256/128 L/S a core and 128bit SIMD units just like Bulldozer. Big high ILP throughput SIMD style workloads aren't going to see the same level of performance improvement per core as regular branchy lower ILP code.

If 256/128 L/S a core is true than that does spell not much good for AVX1/2. That would be a major disappointment.

Regarding the 40% IPC increase. Everybody seems to assume this is for single threading.
Did AMD explicitly state this?
As Zen will do SMT it could just as well be 10% increase for single thread + 30% increase instructions per clock when using multiple threads, for a single core.
 
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