Different parts of the equation. OpenCAPI providing the hardware/network layer and a technology parallel to that Intel queuing one I linked the software synchronization layer.
Is this something mentioned in the documents for OpenCAPI, or is this something you predict will happen? I find it more difficult to discuss statements whose tense and grounding in fact/assertion are ambiguous.
You have what I said backwards.
The statement was that the signalling standards are the same.
I would accept having a true/false backwards if there's a reference to this, perhaps one that explains the common basis not showing through their differing behavior.
The control and data fabrics using essentially the same lanes based on configuration.
I'd have to dredge up the EPYC presentation/video where they indicate the control and data fabrics do not share lanes.
The bandwidth and latency needs are more relaxed, meaning that there's a minor connection carried between EPYC dies that carries control information. I don't quite recall the statement, but its connectivity requirements are such that it isn't a fully-connected setup like the MCM or a mesh. Could be a ring or potentially daisy-chained since the time period for functions like the on-die DVFS controller is in the millisecond range.
It's minor enough that they don't clutter the big-ticket data fabric diagrams with it.
As I said above, the opposite. It would always encompass the PCIe standard from a hardware aspect. Think infinity switch and PCIe switch on each chip with a configuration setting determining what lanes went where. That may only apply to half the links on any given chip to conserve space.
Is there a reference to Infinity Fabric being a superset of the PCIe standard? There appear to be different physical restrictions and portions of the PCIe standard AMD doesn't claim to offer for its fabric. The Processor Programming Reference for family 17h diagrams separate elements for PCIe and xGMI at the physical layer, so there's a physical partition just before the shared muxed PHY (third-party Synopsis E12G IP, I think). Prior to that there are PCIe specific paths that hang from the southbridge, whereas the xGMI physical layer hangs from the data fabric.
While Hypertransport was originally defined to use the PCI (the original) ordering model and maintains its conventions, I haven't seen it described that PCIe has become a subset of either HT or IF despite PCIe being a superset of PCI.
