AMD: RDNA 3 Speculation, Rumours and Discussion

Discussion in 'Architecture and Products' started by Jawed, Oct 28, 2020.

  1. ToTTenTranz

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    Each chiplet seems to be able to function in a fully autonomous way. They all have their own memory PHY, set of fixed function blocks (probably video codecs?), and they communicate with each other through the L3.

    To me this looks a bit like first-gen Zen but in a GPU. It also means there could be a lot of wasted space due to a bunch of fixed-function blocks being replicated and useless for all chiplets but one. Though if they could get the video codecs to work in parallel it would be awesome, especially if more chiplets = higher resolution or higher framerate encoding).
     
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  2. Rootax

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    Won't you waste space with MCM solutions ? I mean you still need the transistors for compute functions, etc, but now you need to have more external buses to make the multiples parts of the chip communicate between them ? I'm sure I'm missing something here. Or it's "just" about yield ?
     
  3. Jawed

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    In the end, with Ryzen, it was about going way past the conventional reticle limit in terms of transistor count. It also helped yield.

    HBX will cost power and power is going to be a pain point for huge transistor counts. Look at Threadripper 3990X versus any Ryzen.

    One thing that's not clear is the effect of Infinity Cache on power usage. We don't have a good "performance equivalent" estimator and probably never will. Some of that huge transistor count that chiplets allows for might simply be to increase the size of Infinity Cache.
     
  4. ToTTenTranz

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    Not just yield but also versatility on using the same chip for a multitude of SKUs and performance ranges, the economy of scale achieved by it, and the money saved by developing only one chip.
     
  5. CarstenS

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