AMD: RDNA 3 Speculation, Rumours and Discussion

So more than one cache die? Because with one alone, 512 Mbytes of cache on N6 Will take anyway a lot of space

 

No shit.
Why fab big when you're slicing your interleaving your LLC slices anyway.

Well kinda the point.
They won't take that much less space on N5 so N6 it is.

 

But having two separate cache dies means all this will need one more level of stacking (another die for Memory and I/O?) for inter-die bandwidth interconnect. So one MCD, two cache dies and two GCDs?

 

There are none.
MCDs are the cache dies.

Two GCD and fuckton of MCD.

 

Ah, ok. It makes me wonder how the inter-die interconnection will work, in that case. So if we have i.e. 4 64-bit memory channels each attached to a 128 Mbytes cache, all these will be shared between the two GCDs (thus insuring high inter-die bandwidth) or are they separated, and inter-GCD communication goes over something else? Also, even if this is a premium product, is not stacking a lot of dies reducing the yields someway?

 

But we don't.

yes.
You add MCDs you scale the bandwidth up, be it interdie, LLC, offchip, you name it.

 

Then will N33 aim only at FHD gamers with that kind of performance? There are already examples, where 8GB Vram limits RTX 3070's performance, at least when you also enable RT effects.

 

Yea or 1440p if you're lucky.

 

N33 should be a lot faster than N22, right?

 

Yea.

 

I don't see a point in a mobile(desktop) GPU, which is a lot faster than RX 6800m, but will have less Vram and at best be aimed at 1440p. If the price wasn't high, then ok, but It looks like It will be quite high.

 

Someone's gotta drive them HRR panels.

Of course.
Premium brand things.

 

If the goal is to overcome the rectile limit, adds gigantic amount of caches, while also taking advantage of the chiplet economies of scale, one big boy MCD seems to be the weakest link of the story, even if it is made on an older process.

One other possibility is a more exotic setup like TSMC SoIC, with one upper die being bond to multiple lower dies. Say hypothetically it could be a 3-layer stack: 4 MCDs with off-chip I/O (GDDRx, SerDes, power, etc) at the bottom layer; 2 GCDs in the middle, each bound to a MCD pair; and at the top an (passive?) interconnect die to link both GCDs together, with enough bidirectional bandwidth to maintain the performance profile of interleaved uniform memory.

 

ugh AMD is the only ones using it till forever.
duh.

Only 2-hi for now.

 

Does the MCD have cache and memory controllers on same die ?

And what's about ray tracing ? BVH acceleration as well ? And something beyond that maybe?

 

Yep!

Still part of the WGP.

No one knows.

 

Incredible that there are posts daily for a product that at best would launch in 15 months.
No new info, no mention at the slightest from AMD ...

 

I think there's plenty of new info in the last ~20 pages.
In fact, this weekend had lots of articles on Navi 3x based on tweets and.. this thread.

 

Why would they ever.
Even shipping shit like MI200 doesn't currently exist as a product.

 

This one i don't get it. First mcm GPU shipping and silence like sh...