davis.anthony
Veteran
I wonder what the costs are between running a large memory bus with GDDR6/X and a high amount of internal cache vs just using HBM3.
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Cache capacity is just one factor that drives effective hit rate. If anything, all hit rate graphs are bound to the specific context of how one particular architecture makes use of that one level of cache hierarchy. It is useful to predict how different SKUs of the same architecture performs, but never a good portable performance predictor across generations of architectures, where you probably expect significant changes everywhere over one another.
To make the grand assertion of yours at this point of time, you are basically saying ceteris paribus i.e. nothing else outside the Infinity Cache has changed. Like no cache policy changes, no access pattern optimisation, no change to L0 or GL1, no improvements to RBE/DCC, etc. There is simply no information.
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For cost efficiency one wants to reuse the MCD die across all models. An increase of the MCD integrated cache that appears to be justifiable if one looks solely at N31, may not be looking very appealing for smaller models. But on the other hand, the price AMD can achieve for the fastest version of N31 might justify the additional cost of stacking some additional cache dies. At the high end, the price/performance ratio is far from linear. Even relatively small performance increases at the top justify relatively larger cost increases for the manufacturer. That is not the case at the low end. Furthermore, stacking cache increases the cache size by a multiple, not just a small increment, so it ends up with a way bigger return (in terms of performance) than just a moderately larger cache on all MCDs.
In other words: Increasing the cache integrated in the MCD increases the cost across the complete range of products, which may be as cost inefficient as increasing the L3 in all AMD CPUs (instead of just using a cache stack on the 5800X3D). Using stacking only in an enthusiast model AMD incurs the associated costs only for this model. So the situation with RDNA3 may in fact not that different.
Upcoming RDNA 3 GPUs are presumably RX 7000 desktop GPUs. RX 6000 is RDNA 2.
Yeah, I've wondered along those lines too. The expected design for the high end is a big GPU surrounded by 6 chiplets which house L3 cache and memory controllers and PHYs, all sitting on an interposer.
So, 6 chiplets + 24GB* Gddr6 versus 16GB HBM2 (not sure HBM3 is ready enough).
* I think it's safe to say the 24GB is all about the bandwidth (and maybe some marketing) and not so much about the storage capacity. I don't think we're anywhere near the point of using that much memory and it's not going to help with the benchmarks.
Jawed
Legend
According to the patent application:
DIE STACKING FOR MODULAR PARALLEL PROCESSORS - ADVANCED MICRO DEVICES, INC.
<div p-id="p-0001">A multi-die parallel processor semiconductor package includes a first base IC die including a first plurality of virtual compute dies 3D stacked on top of the first base IC die. A f
www.freepatentsonline.com
the chiplet that provides cache and memory connections, the "active interposer die" is not the kind of interposer that was seen with HBM-based GPUs. For a start it actually has logic in it, it's not just providing power and connectivity for the chips that sit upon it.
Notice there is no "MCD" in that document. This is why I think the leakers are clueless about the actual package, its chiplets and the stacking.
Bondrewd
Veteran
Ah that's for CDNA3 and onwards.
A lot actually.
It's gfx11 now, remember?
gamervivek
Regular
Wishing for a 8SE 16384 shaders 420mm2 chip(GCD)
More SIMDs in a workgroup processor.
I have a feeling this is gonna turn in to a huge advantage for AMD this cycle. 
I think it's going to be largely irrelevant overall, especially considering the issues are likely a very small number of people who buy 4090's, which in itself will be a very tiny portion of PC enthusiasts.I have a feeling this is gonna turn in to a huge advantage for AMD this cycle.
I think it'll overshadow the whole 4000 series and will loom large over nVidia for this generation, but it'll be interesting to see either way.
Much worse things haven’t hurt Nvidia so I doubt this time will be different. Most of the noise seems to be coming from tubers and not actual users so it’s unclear if many people are actually affected. Either way, some piss poor engineering there.
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