AMD: R7xx Speculation

[randomhack]

Rage3d has their architecture overview up:

http://www.rage3d.com/reviews/video/atirv770/architecture/

That shot of all the die on a wafer is just pure sex... beautiful!

Thanks for the link. That was an excellent review. As a GPGPU guy, waiting for new CAL release that exposes that global data share.

edit : No info about "local data share" though. Anyone have any info/links on that?

 

[Jawed]

Awesome summary Rys.

*** ^infinity, that's honestly the best thing ever

And that really is the dog's danglies. Courtesy of some crazy rabbits, apparently.

Jawed

 

[Lukfi]

=>ZerazaX: As a journalist, I happen to have those pics too. You want the wafer in a 4080x4080 rez in PNG?

 

[Jawed]

Where the heck are the texcoords interpolated? Odd that it doesn't scale with SIMD count.

In that unit called Interpolators. Then stuffed into a cache, I believe, for use as fragments are rasterised and coordinates despatched for the TU to pre-fetch.

Jawed

 

[Jawed]

Maybe the rate at which samples can be fed back to the shader is limited.

Or maybe the rate is constrained by the RBEs having to send samples to the ALUs and receive completed pixels from the ALUs at the same time?

If so, I wonder if this also applied in R6xx?

Jawed

 

[ZerazaX]

If you can put those pics somewhere, that would be awesome!

 

[AnarchX]

Oh, interessting bit of information @ Rage3D:

Fillrate

We've tested the RV770's fillrate with a number of apps, and always came up with numbers in the (19,20) GigaTexel interval...too low for a 10 TU/40 TA&TF part - should be near the 25 GigaTexel mark (625*40/1000). For all those of you who cried "FOUL!", relax for a bit - we actually went and asked ATi why we were getting this behavior and they explained that in spite of having 10 TUs on chip, there are only 32 bilinear interpolators, so the INT8 bilinear rate will be limited by that. Once you get filtering limited, with Anisotropic Filtering, or by filtering FP textures, the architecture should behave like a 10 TU part. We've verified this using FP texturing, because that has also allowed us to check the assumption that the RV770 does FP filtering at half-rate

 

[A.L.M.]

Interesting how Anandtech shows 8800GT load consumption lower than 3870 load while HardOCP shows about the same.

I think it depends from the definition of load consumption.

 

[Sunday]

I haven't noticed that any review payed attention to new and improved UVD capabilities... such a shame! Dave had excellent presentation about it!
Great work Dave!

 

[AlphaWolf]

I haven't noticed that any review payed attention to new and improved UVD capabilities... such a shame! Dave had excellent presentation about it!
Great work Dave!

Hothardware.com was the only site that even mentioned UVD I think, and I wouldn't exactly call it in depth.

 

[A.L.M.]

Here's another interesting bit of information from the Anandtech review:

Although AMD isn't talking about it now, the CrossFire Sideport is a new feature of the RV770 architecture that isn't in use on the RV770 at all. In future, single-card, multi-GPU solutions (*cough* R700) this interface will be used to communicate between adjacent GPUs - in theory allowing for better scaling with CrossFire. We'll be able to test this shortly as AMD is quickly readying its dual-GPU RV770 card under the R700 codename.

What could it mean?
Now, through CF-X connecting lanes printed on the PCB, what kind of "communication" is there between the two gpus that are in a HD3870X2, for example?
And what is the current bandwidth of a CF-X connection like that?

Because it seems that through this sideport the second gpu could actually be able to share some of the other gpu resources, like framebuffer, or something else...

 

[roadie]

Oh, interesting bit of information @ Rage3D:
Fillrate

We've tested the RV770's fillrate with a number of apps, and always came up with numbers in the (19,20) GigaTexel interval...too low for a 10 TU/40 TA&TF part - should be near the 25 GigaTexel mark (625*40/1000). For all those of you who cried "FOUL!", relax for a bit - we actually went and asked ATi why we were getting this behavior and they explained that in spite of having 10 TUs on chip, there are only 32 bilinear interpolators, so the INT8 bilinear rate will be limited by that. Once you get filtering limited, with Anisotropic Filtering, or by filtering FP textures, the architecture should behave like a 10 TU part. We've verified this using FP texturing, because that has also allowed us to check the assumption that the RV770 does FP filtering at half-rate

I too find this interesting. I am assuming that the chip is optimised for 16xAF. If it isn't, why not?

 

[Rangers]

It's a great chip. especially given it's size of course, but I have a hard time calling an upper-mid range card too many superlatives. If it were the absolute perfomance leader by more than 50% or something crazy like that, maybe.

But I often recall what Nvidia said about the competition in a transcription of a recent conference call posted right here at B3D. They said that current day ATI/AMD and them are the "two best GPU companies in history". That showed me they have a lot of respect for ATI.

 

[MfA]

I'm assuming the present Crossfire-X connection simply ties the two display controllers together. The bandwidth it has wouldn't really be relevant here if what Anand says is an accurate representation of what AMD said. The Crossfire sideport would use different pins.

 

[A.L.M.]

I'm assuming the present Crossfire-X connection simply ties the two display controllers together. The bandwidth it has wouldn't really be relevant here if what Anand says is an accurate representation of what AMD said. The Crossfire sideport would use different pins.

Ok, but what kind of information two cards share through a normal crossfire? Only things related to the - let's call it - "AFR queue" or also something else? 'Cause I suppose that a connection that basically connects directly one gpu to the "distributed MC" hub of the other, and viceversa, is something very different from a normal CF connection, isn't it?

 

[hoom]

Hexus review says the/a ringbus does still exist & is the link between L1/Vertex cache & L2/MC/ROPs :smile:

 

[MfA]

Ok, but what kind of information two cards share through a normal crossfire?

Framebuffer content for video out.

 

[mboeller]

I'm assuming the present Crossfire-X connection simply ties the two display controllers together. The bandwidth it has wouldn't really be relevant here if what Anand says is an accurate representation of what AMD said. The Crossfire sideport would use different pins.

Maybe this is one of the rabbits CJ mentioned?

 

[liolio]

Here a link that point to AMD presentation about the R77O:
http://www.pcinpact.com/actu/news/44386-Radeon-HD-4850-4870.htm

Between there is a presentation by our dear Dave

 

[mczak]

My specials rate is wrong, only the fatter unit can do that (corrected that too). Integer for them all though.

Sorry but I still don't believe there were many changes there. Even R600 could apparently do int32 add in the slim alus, and other reviews only mention that int32 shifts have been added (which are very cheap to implement), but otherwise I haven't seen anything which would indicate they now can do int32 mul (or mad). Though maybe they can do int->fp conversion, so as long as the ints are below 24 bits it may work...