AMD: R7xx Speculation
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Bouncing Zabaglione Bros.
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Anarchist4000
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The obvious assumption is that there is some form of high speed interconnect between the hubs on both chips. What I'd like to know is just how much bandwidth that connection has because that would seem to be the major bottleneck.
The odd thing is that the setup looks almost identical to the memory controllers used by AMD's quad cores.
Yeah it seems increasingly likely that G200 is going to be the largest monolithic GPU for a few years at least.
In a way I feel like ATI's new strategy was bold and this was the first time we actually had both teams release their cards on time (shocking for ATI, i know) and the first time ATI had this strategy right from the beginning of a new generation (RV670 vs G92 doesnt count since they were just die shrink refreshes of existing monolithic GPUs). In a lot of ways it makes sense - ATI can easily convert the RV770 architecture to mobile GPU's while G200 probably never will until its cut down and shrunk considerably. Cutting down RV770 to RV710, RV730, etc. will not be that hard either if the rumors that the architecture is very modular and scalabe are true.
Nvidia's approach of releasing a monolithic high-end GPU then later bringing in derivaties of smaller GPUs (like G80 came first then we had G84 and G86) may be in trouble because it seems like Nvidia has different teams focused on each set, and G84 and G86 were terrible in comparison. I'm sure there are G200 derivatives for the midrange on the way, but with word that the G92 design will be used for another year or so, it remains to be seen whether these cards can face off against RV770 still.
Anyways as pointed out by Jawed a few times, the next shrink that becomes available from TSMC is likey to be 40nm (if they skip 45nm) by sometime early next year can see a RV770 derivative (maybe RV870) with some ridiculous numbers in the same die space. R600 architecture was supposed to last at least 3 generations so R800 series we might see some gigantic numbers if they're on the 40nm process.
In a way I feel like ATI's new strategy was bold and this was the first time we actually had both teams release their cards on time (shocking for ATI, i know) and the first time ATI had this strategy right from the beginning of a new generation (RV670 vs G92 doesnt count since they were just die shrink refreshes of existing monolithic GPUs). In a lot of ways it makes sense - ATI can easily convert the RV770 architecture to mobile GPU's while G200 probably never will until its cut down and shrunk considerably. Cutting down RV770 to RV710, RV730, etc. will not be that hard either if the rumors that the architecture is very modular and scalabe are true.
Nvidia's approach of releasing a monolithic high-end GPU then later bringing in derivaties of smaller GPUs (like G80 came first then we had G84 and G86) may be in trouble because it seems like Nvidia has different teams focused on each set, and G84 and G86 were terrible in comparison. I'm sure there are G200 derivatives for the midrange on the way, but with word that the G92 design will be used for another year or so, it remains to be seen whether these cards can face off against RV770 still.
Anyways as pointed out by Jawed a few times, the next shrink that becomes available from TSMC is likey to be 40nm (if they skip 45nm) by sometime early next year can see a RV770 derivative (maybe RV870) with some ridiculous numbers in the same die space. R600 architecture was supposed to last at least 3 generations so R800 series we might see some gigantic numbers if they're on the 40nm process.
Not right now...Hey, isn't that Dave's job
Jawed
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http://eetimes.com/news/latest/show...XITDCIQSNDLRSKH0CJUNN2JVN?articleID=208404063
Seems to me this was a decision made before AMD came on the scene.
AMD hasn't chosen to stop making halo graphics cards - it's decided to make them with 2 GPU chips.
Jawed
I'd give anything for there to be another architect interview at B3d like the R600 one, though that may have been an anomaly. What happened with the ring bus? Was it too overloaded, too unnecessary, too much of a pain to optimize?
Extremetech needs to fix its diagram too, otherwise RV770 has 1600 ALUs.
The Data Request Bus is poorly defined. It must link all the texture caches to each SIMD array's TMU, but it also has to link the vertex cache and global data share to everything else.
It would have been called a crossbar if it was one, wouldn't it?
What is it then, if not a crossbar, a switch fabric, ring bus?
Extremetech needs to fix its diagram too, otherwise RV770 has 1600 ALUs.
The Data Request Bus is poorly defined. It must link all the texture caches to each SIMD array's TMU, but it also has to link the vertex cache and global data share to everything else.
It would have been called a crossbar if it was one, wouldn't it?
What is it then, if not a crossbar, a switch fabric, ring bus?
Anand's numbers are out:
http://www.anandtech.com/video/showdoc.aspx?i=3338
I don't really like their take on the GTX+, but that's me.
http://www.anandtech.com/video/showdoc.aspx?i=3338
I don't really like their take on the GTX+, but that's me.
Well the GTX+ better fix the issues with increased AA and resolutions or otherwise the 4850, which seems to take far fewer hits than the 9800GTX, will still be the better solution if you love AA and AF and resolution at that price bracket.
Now I really want to see what the 4870 can do though
Now I really want to see what the 4870 can do though
Jawed
Legend
LOL, so the memory system is still fully distributed but no longer has the form of a ring
Moving the L2s closer to the MCs is, of course, very similar to what NVidia has (identical?). The hub in RV770 is much like the crossbar in G8x and later, twixt texture clusters and ROP partitions.
The difference between the two designs appears to be that the hub is not involved in completed fragments arriving in the RBEs - there is seemingly a separate path, via Shader Export, directly to the RBEs.
Though with NVidia's GPUs we don't know if there's a single crossbar between clusters and partitions or whether there's one for texture data and a separate one for fragments.
So AMD seems to have chosen to match RBE count and MC count (RV560/570, RV630/635 being the obvious exceptions) - which means that colour/z/stencil performance looks like it'll only scale with GPU-count and clock.
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Huh? four-thirds! For some reason the article is written on the basis that RV670 is 480 ALU lanes.
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Can anyone work out what specifically was done to make the ALUs smaller?
Jawed
Bouncing Zabaglione Bros.
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It's quite possible that ATI can make a 4870x2 to take the performance crown (and do it cheaper, cooler and with less power than it's monolithic competiton), while Nvidia simply can't make a G280x2. Right there you can see the advantages of going multicore demonstrated in the form of a product that's viable verses a product that isn't.
ATI decided to get out of that dead-end early (and paid for it over the last couple of chip generations) while Nvidia tried to stick it out with monolithics for as long as possible - but it's put them behind on their next steps towards multi-GPU.
The extremetech diagram kind of conflicts with the other block diagram from pcinlife.
The the data request bus is listed as a crossbar, and the pcinlife diagram has no direct mention of the crossbar between the L2 caches and the L1s.
I'm also seeing no mention of that memory read/write cache in the extremetech diagram.
The the data request bus is listed as a crossbar, and the pcinlife diagram has no direct mention of the crossbar between the L2 caches and the L1s.
I'm also seeing no mention of that memory read/write cache in the extremetech diagram.
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