It should be, as the video and the ideas are part of the CINEMA 2.0 presentation.
Big question is, when is AMD going to put that one up.
Hell.. 2.0 is so much better than HD.
AMD: R7xx Speculation
- Thread starter Unknown Soldier
- Start date
- Status
It should be, as the video and the ideas are part of the CINEMA 2.0 presentation.
Big question is, when is AMD going to put that one up.
Hell.. 2.0 is so much better than HD.
Jawed
Legend
Wow, I thought you were home and dry with 800.
As far as density goes I have to say the ALUs are the least of my queries. The actual math part should be small anyway, and gobs of register file are very dense. It's a question of the scheduling hardware and buses linking it all together.
The thing that's surprising is the TU count, even if that diagram implies they've been trimmed down.
I realise, though, that you're working on the basis that that diagram is fake.
Jawed
Jawed
Legend
If G92, 9800GTX, is bandwidth-bound, why shouldn't HD4850 also be bandwidth bound, particularly as it has less bandwidth?
Jawed
DegustatoR
Legend
4870 is bandwidth-bound too? Last i heard they're putting it against 9800GTX which is still G92.
Jawed
Legend
I thought you were referring to actual tests with HD4850 that's out in the wild, not to AMD's slides.
Hmm, now they have GTX260 performance figures maybe they'll put it against that? Maybe they won't if it's notably slower, guess we'll just have to wait.
Jawed
Nebuchadnezzar
Legend
http://imageupload.com/out.php/i129466_mayberv770.jpg
Upsized from http://pc.watch.impress.co.jp/docs/2008/0617/amd_01.jpg at http://translate.google.co.jp/trans.../2008/0617/amd.htm&sl=ja&tl=en&hl=ja&ie=UTF-8
If that is RV770, then it would support that last slide, turn the chip 90° and you clearly see 10 rows of processors, although the pic is too small to make out the outlines of the processors themselves.
Upsized from http://pc.watch.impress.co.jp/docs/2008/0617/amd_01.jpg at http://translate.google.co.jp/trans.../2008/0617/amd.htm&sl=ja&tl=en&hl=ja&ie=UTF-8
If that is RV770, then it would support that last slide, turn the chip 90° and you clearly see 10 rows of processors, although the pic is too small to make out the outlines of the processors themselves.
If you read some AMD PR comments you will see that in one article they say that "Nvidia has 240 cores, but AMD has more the 500".
So it will have more then 500 for shure
Maybe 600 or 800.
http://www.eetimes.com/news/latest/showArticle.jhtml?articleID=208404063&pgno=1
I am home and dry imo, because I'm pretty confident they won't talk about shader clocks and the number of real units in the marketing docs. The only way I could have gotten that data, then, would have been if my source was one of ATI's lead engineers - sadly, that's not the case. Ah well, maybe next time?
I don't agree, I know more than enough about the rest of the semiconductor industry to know that many engineers would gaze in awe if they truly managed to fit in 800 FPUs in only 250-270mm² given that it's far from 100% of the die, there's a bunch of extra control logic & large register files and, well, one or two extra things I can't mention that make it even more impressive.
The TU count is surprising for ATI, because their TUs have been a joke ever since R520. For NVIDIA, on the other hand, that's par for the course; and it's pretty clear, based on that presumably correct leaked information, that their TMUs are much more similar in performance/clock to GT200's than RV670's. A quick estimate tells me that 40 GT200 TMUs on 55nm would cost, at most, 60mm². Not exactly a big obstacle to reach 250-270mm²...
I am not, I am assuming that is probably correct but that it may not represent the physical reality of the chip because it's too marketing-like.
leoneazzurro
Regular
Arun, but in reality they are not 800, they are 160
Good catch. Of course, it's marketing, so once again it might not represent the physical reality of the chip... But if they had 800 SPs physically, you could argue that they would have said "more than three times" instead. Hmmm. As I said, I still find 300 physical ALUs with each being slightly bigger than one from RV670 more believable, but who knows!If you read some AMD PR comments you will see that in one article they say that "Nvidia has 240 cores, but AMD has more the 500".
So it will have more then 500 for shure
Maybe 600 or 800.
Love_In_Rio
Veteran
Awesome
Looks like 10 columns of 4 (each being a quad). At the bottom of each column is the sequencer?
EDIT: hmm, Sequencer + TU?
Jawed
This chip is everything ALUs!
Good catch. Of course, it's marketing, so once again it might not represent the physical reality of the chip... But if they had 800 SPs physically, you could argue that they would have said "more than three times" instead. Hmmm. As I said, I still find 300 physical ALUs with each being slightly bigger than one from RV670 more believable, but who knows!
They are Xenos like ALUs
By the way, has Michael Doggett something to do with this project ?
Last edited by a moderator:
hoom
Veteran
Just regarding the reflections on the cars in that demo: Check out the Toyshop Demo on Follow Taxi mode.
Seems to be rendering several views to MRTs then reading the MRTs as a cube map for teh shiny.
That was an x1800 demo so I'd expect things to have moved on considerably from there by now.
Seems to be rendering several views to MRTs then reading the MRTs as a cube map for teh shiny.
That was an x1800 demo so I'd expect things to have moved on considerably from there by now.
Jawed
Legend
Indeed, where's that coming from?
EDIT: Removed my earlier speculation given that I just saw fellix's image, hmmmm.
CJ @ tweakers.net forum;
16 juni 2008 @ 19:29:
The RV770 has 10 SIMD Arrays of 80 streamprocessors, (160x5. Total 800 SPs)
The RV670 has 4 SIMD Arrays of 80 streamprocessors, ( 64x5. Total 320 SPs)
(dutch)
Trouwens... Aan elke array is een Texture Unit (met 4 TMUs) gekoppeld zoals je kan zien op het plaatje. De RV670 had 4 Texture Units x 4 TMUs = 16 TMUs. De RV770 heeft 10 Texture Units x 4 TMUs =.....
:smile:
- Status
Similar threads
