AMD: R7xx Speculation

[Wirmish]

How did AMD manage to integrate 800 SP + 40 TMUs into a 256~275 mm² chip ?

I would like to believe it, but that seems almost impossible...

 

[DegustatoR]

How did AMD manage to integrate 800 SP + 40 TMUs into a 256~275 mm² chip ?
I would like to believe it, but that seems almost impossible...

They got rid of all the cache? 8)

 

[Slappi]

How did AMD manage to integrate 800 SP + 40 TMUs into a 256~275 mm² chip ?

I would like to believe it, but that seems almost impossible...

They didn't

 

[Wirmish]

Or the chip have 29 layers, and each cache cell can store 4 bits ?!

They didn't

SP ? TMUs ? Both ?

 

[itaru]

How did AMD manage to integrate 800 SP + 40 TMUs into a 256~275 mm² chip ?

I would like to believe it, but that seems almost impossible...

Perhaps 350 mm2

 

[liolio]

It wouldn't explain how ATI fit so many ALU in the chip but I have a question:
could ATI have gone the same way as Intel and use the ALU to do the triangle setup?

 

[Thorburn]

Looks like they must have made nice improvements in that area, but it's interesting that the latest leaked slides from AMD only showed 8xAF. Any reason to believe that there would be a significant performance drop from 8xAF to 16xAF?

Just as a side note when you generate test results for presentations you don't have an infinite amount of time. Trust me!

Benchmark results for external distribution have to follow fairly strict guidelines and procedures to ensure they are accurate and reproduceable.
The labs won't have an infinite number of people working on an infinite number of rigs, tests take time to complete and there are always issues and roadblocks in your way, particularly with pre-release products.

So there is a good chance that 4xAA, 8xAF was used because when the data was needed that is simply the data they had.

 

[itsmydamnation]

or TMU's are a big bottle neck at 16X AF

 

[nAo]

It wouldn't explain how ATI fit so many ALU in the chip but I have a question:
could ATI have gone the same way as Intel and use the ALU to do the triangle setup?

They could but triangle setup probably takes an awful small area of the chip anyway

 

[Tchock]

The PR slides want to showcase the best case scenarios.

I'm guessing that the 16x would dampen the lead, but not till it is gone.

Last round with 16, 4x was the optimal perf/setting balance. This time 16x is probably feasible though.

 

[AnarchX]

Some real-world benchmarks by Chiphell with 16xAF:
http://diybbs.pconline.com.cn/topic.jsp?tid=8725790


I still ask me how the quality will be...

 

[air_ii]

Some real-world benchmarks by Chiphell with 16xAF:
http://diybbs.pconline.com.cn/topic.jsp?tid=8725790


I still ask me how the quality will be...

Interesting how min framerate in WiC increased from 13 @1680x1050 to 18 @1680x1050 4AA 16AF. A bit fishy...

 

[AnarchX]

Interesting how min framerate in WiC increased from 13 @1680x1050 to 18 @1680x1050 4AA 16AF. A bit fishy...

You know what Min-FPS are and how reliable they are?

 

[whocares]

Which driver is used for HD4850 testing ? 8.5 isn't supporting RV770s cards .

 

[Mat3]

http://www.tgdaily.com/html_tmp/content-view-37907-135.html
AMD’s physics secret revealed: It’s Havok

The two companies said that they are also “investigating” the use of “AMD’s
massively parallel ATI Radeon GPUs to manage appropriate aspects of physical
world simulation in the future.”

I was excited when I started reading it, but only "investigating" for the GPUs? Doesn't sound like they're that serious about it.

 

[no-X]

How did AMD manage to integrate 800 SP + 40 TMUs into a 256~275 mm² chip ?

I would like to believe it, but that seems almost impossible...

3DM06 multi:
HD4850: ~ 19800
HD3870: ~ 12300

anyone else, who is still expecting 40 TMUs?

 

[Jawed]

HD4850: ~ 19800 = 99% of theoretical, 32*625
HD3870: ~ 12300 = 99% of theoretical, 16*777

Jawed

 

[trinibwoy]

3DM06 multi:
HD4850: ~ 19800
HD3870: ~ 12300

anyone else, who is still expecting 40 TMUs?

32 TMUs and 800 ALUs is still mighty impressive. I completely underestimated the kind of density AMD could achieve. Especially if it's still only 16 5D shaders per processor.

 

[Jawed]

32 TMUs and 800 ALUs is still mighty impressive. I completely underestimated the kind of density AMD could achieve.

Hey, don't forget the extra MSAA capability. We don't know what it is yet, but I really can't see any alternative to there being extra Z test hardware.

Jawed

 

[trinibwoy]

Heh, you know one lesson we should all learn from this episode?

ALWAYS TRUST THE CHINESE!!