I'm leery of trying to extrapolate too much from AMD-provided "die shots" given the fuzziness and what AMD has done before when it comes to manipulating pre-launch pictures.
I tried to compare with DDR4 interfaces elsewhere like Haswell E, and some comparisons in MS paint could put the rough area of a single interface+controlling logic around 11mm2, and if we assume the perspective correction and area are accurate for the AMD picture, it's .06 of the image and could put it around 180-200mm2, with huge error bars.
edit: I was using the annotated picture and stupidly forgot to take the heading out.
With that done the range is above/below ~180mm2, still with huge error bars either way.
That might put the core area in that annotated diagram in the ~5mm2 range. In comparison, it seems like a Skylake core in the 6700k might be in the ~8mm2 range. That's including the L2 and a potentially larger vector unit. The "L2" for Zen would be in the 1-1.5mm2 range.
(edit: Correcting for the earlier error puts the core in 4-5mm2 range.)
At least at first glance, the way the core and L2 and L3 areas are annotated seems plausible.
The way the broader wafer shot draws the cuts actually seems off to me. There's more spanning the black line between the left side of a core cluster and the silicon on the right side of the other die, rather than the expanse in the middle.
I'm assuming the bright areas that form the asymmetric grid of the L3 represent parts where data bus lines have to hit higher metal layers, and similarly bright areas in the core areas are related to congested portions of the core like the front end and caches. (edit: interfaces with caches)
The asymmetry of the L3 might come from not needing its full width to route the L3 and coherent interconnect through/over the core complex
As for whether this is an upscaled Jaguar cluster. At least right now, I'd say not quite. Jaguar's LLC was an L2 that was separated from the cores by a big unified interface. I'm not sure this is the case even within a cluster, and the L2s as labeled are tied to the cores.
edit: Since I'm making edits. What would the benefit be in having the DDR4 interface put on both sides of the die? Nobody else seems to have a problem with putting memory on one side and not crowding other connections.
I tried to compare with DDR4 interfaces elsewhere like Haswell E, and some comparisons in MS paint could put the rough area of a single interface+controlling logic around 11mm2, and if we assume the perspective correction and area are accurate for the AMD picture, it's .06 of the image and could put it around 180-200mm2, with huge error bars.
edit: I was using the annotated picture and stupidly forgot to take the heading out.
With that done the range is above/below ~180mm2, still with huge error bars either way.
That might put the core area in that annotated diagram in the ~5mm2 range. In comparison, it seems like a Skylake core in the 6700k might be in the ~8mm2 range. That's including the L2 and a potentially larger vector unit. The "L2" for Zen would be in the 1-1.5mm2 range.
(edit: Correcting for the earlier error puts the core in 4-5mm2 range.)
At least at first glance, the way the core and L2 and L3 areas are annotated seems plausible.
The way the broader wafer shot draws the cuts actually seems off to me. There's more spanning the black line between the left side of a core cluster and the silicon on the right side of the other die, rather than the expanse in the middle.
I'm assuming the bright areas that form the asymmetric grid of the L3 represent parts where data bus lines have to hit higher metal layers, and similarly bright areas in the core areas are related to congested portions of the core like the front end and caches. (edit: interfaces with caches)
The asymmetry of the L3 might come from not needing its full width to route the L3 and coherent interconnect through/over the core complex
As for whether this is an upscaled Jaguar cluster. At least right now, I'd say not quite. Jaguar's LLC was an L2 that was separated from the cores by a big unified interface. I'm not sure this is the case even within a cluster, and the L2s as labeled are tied to the cores.
edit: Since I'm making edits. What would the benefit be in having the DDR4 interface put on both sides of the die? Nobody else seems to have a problem with putting memory on one side and not crowding other connections.
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