A wild Intel discrete GPU appears

[Deleted member 13524]

https://www.notebookcheck.net/Intel-reveals-prototype-of-their-discrete-GPU.284754.0.html

Original slides from here:

https://pc.watch.impress.co.jp/docs/column/kaigai/1107078.html

It's a small 64mm^2 chip with 1.5B transistors.

They seem to show the ability to turn on/off selected Execution Units and control their clocks independently of the fixed function parts of the GPU.

 

[3dilettante]

The focus of the presentation is around the fine-grained clock and voltage management, and how to best manage a more heterogeneous SOC.

There are elements to this with some similarities to a few of AMD's DOE research into power-efficient compute. Patents for that include lane or unit clock and voltage regulation.
The lower bound of Intel's prototype voltage and clock does seem reminiscent of its NTV CPU at 32nm.
https://www.realworldtech.com/near-threshold-voltage/2/
And then GPU prototyping at 22nm, with similar DOE research:
https://www.techspot.com/news/55614-intel-labs-details-their-low-power-gpu-core.html

Not sure about mentioning Koduri or focusing on the discrete angle in various news stories.
It's a bit late in the chip design/assembly process to give a hire from a few months ago much to do other than get the chip back from the lab, and the prior prototype GPU was also discrete, since function as a product was not relevant. The silicon techniques and design elements might flow into a future product, but this is too late in terms of hardware features not related to DVFS.
Perhaps someday another step towards complex integration would be to create a prototype at 10nm or lower that has a GPU and CPU with the next round of low-voltage methods plugged in, if needed to push the envelope in aggressive management.

 

[Infinisearch]

Am I reading that slide right when I see 400mhz is it peak clock speed?

edit - also I understand this is a prototype but realistically how much clock speed can be expected from a final product? I've never seen data on a prototype before so I have no idea what kind of scaling could potentially happen with a more final product.

 

[Ryan Smith]

Am I reading that slide right when I see 400mhz is it peak clock speed?

edit - also I understand this is a prototype but realistically how much clock speed can be expected from a final product? I've never seen data on a prototype before so I have no idea what kind of scaling could potentially happen with a more final product.

It's not a design intended for commercial use. So the clockspeed isn't really relevant beyond what Intel needs to hit for research purposes.

 

[Infinisearch]

It's not a design intended for commercial use. So the clockspeed isn't really relevant beyond what Intel needs to hit for research purposes.

Don't they have cycle accurate simulators for that kind of stuff? What would be the point of making a chip with no regards to clock speed?

 

[digitalwanderer]

Larab.....nah.

 

[Picao84]

Larab.....nah.

Well, Larabee was using old fashioned x86. This seems to be more of a traditional GPU.

 

[digitalwanderer]

Well, Larabee was using old fashioned x86. This seems to be more of a traditional GPU.

Well then would we add a "2", "II", or "FINALLY!"?

 

[3dilettante]

Don't they have cycle accurate simulators for that kind of stuff? What would be the point of making a chip with no regards to clock speed?

It's a proof of concept design of new physical implementation, DVFS, and circuit techniques which ostensibly would provide the data that would be needed to be able to accurately model the behavior of said techniques.
The NTV research seemed to point to trade-offs needed for operation at that low voltage realm that could impact performance at the higher end, which might make the upper range less critical once the emphasis has been chosen.
The higher speeds do often mean more physical optimization, which is an investment of resources typically reserved for where it pays off the most for products, and the catch-22 of wanting to know what optimizations work for heretofore unknown circuit methods could come into play.

I'm also somewhat curious how often these proofs of concept make it to a product, or are expected to make it into a product in the near-term.
A fair number of the blue-sky HPC proofs of concept are under the auspices of DOE grant programs and exascale initiatives. That's something of a long-term play, and the vendors may conclude that after the research (and getting the grant) that they aren't in a hurry to use it. The federal project that tosses a bone to marginal or connected players is also a thing, although I'm not sure about here.