I did so when it was published, and I'm well aware of the concept of procedural synthesis. In fact I wrote a fractal tree generator onceJawed said:You need to read that ArsTechnica article linked above.
Sure, but while that does reduce the amount of main RAM bandwidth needed to load models (perhaps drastically), it does not change the fact that only around there's only 22 GB/s of bandwidth to external RAM for all of XB360.Jawed said:The bottleneck you allude to would be arrived at simply by entirely ignoring the procedural synthesis feature that links Xenon and Xenos - it's there to save vast amounts (10s of GB) of bandwidth. 10.8GB/s from CPU-GPU is the equivalent of 21.6GB/s CPU-RAM-GPU.
I'm sure that it can (though I don't recall explicit confirmation), and it's 35 GB/s between Cell and RSX -[edit]- though you may be referring to just write bandwidth, which would actually make more sense in this context. Just forget the last sentenceJawed said:I fully expect Cell/RSX to work the same way, for what it's worth. Though I'm not aware of confirmation, as yet, that vertex/texture data from Cell can be sent to RSX without going via RAM (either XDR or GDDR3). But the 20GB/s bandwidth from Cell to RSX sounds ideal.