Don't agree with that. XeCPU has 1 MB cache. If one core is doing procedural processing say, it could lock out a portion of cache for streaming data. It only needs a little buffer space so can get by with say 32 kb. That leaves 984 KB between two cores. There's nothing saying the partitioning of cache has to be uniform.ihamoitc2005 said:CPU: CELL has maximum of 9 usable hardware threads (2 PPE, 7 SPE) with 256k "cache"/thread but Xenon has only 4 with 256k cache/thread. Use of additional available hardware threads or blocked cache method on Xenon for streaming compressed data for GPU = even less usable cache for sharing by remaining threads and higher instability and perhaps lower overall performance.