Full memory compression keeps the entire memory compressed (with the possible exception of some specialized regions such as DMA). In order to localize the changes needed to support compressed memory, the O/S initializes the system with certain amount of uncompressed memory (e.g., twice the physical memory) and all accesses are to this real address space. The accessed addresses are eventually converted to the compressed space addresses (physical address space) by the memory controller before the actual access is initiated. The access would retrieve the compressed memory block, decompress it and provide it to the processor. Since decompression is a slow process, acceptable performance requires a chipset cache that maintains the recently used uncompressed data. FMC is best illustrated by IBM’s MXT (memory extension technology) that includes the following components [ibm-mxt, pinnacle]:
1. 32 MB of fast (SRAM) chipset cache.
2. Memory compressed in blocks of 1 KB size. Compressed blocks are stored using 1-4 segments, each of size 256 bytes.
3. A compressed block is accessed via a header entry that contains pointers to the 4 segments and other relevant information. For blocks that compress to 64:1 or better, it also allows for an “immediate data” type of representation (in which case all 4 segment pointers would be null).
4. The chipset provides a hardware compression-decompression unit (henceforth called Codec) based on a variant of the LZ77 compression algorithm [ibm-lz].
5. The chipset also provides the TLB (similar to paging TLB) for address translation between real and physical address spaces.
