Xbox One (Durango) Technical hardware investigation

[MrFox]

9/8 ECC on the 32MB SRAM would add up everything to 47MB, but then they wouldn't have said it's 8MB per bank in one slide, and then count the ECC bits in the other.

 

[McHuj]

Do we know what 28nm process Kabini is manufactured on?

I'm just wondering if it's 28nm HPM like the Xbox One SOC. I can't find anything on it. At least public, TSMC said that Snapdragon 800 was the first SOC to use the process.

 

[Exophase]

9/8 ECC on the 32MB SRAM would add up everything to 47MB, but then they wouldn't have said it's 8MB per bank in one slide, and then count the ECC bits in the other.

That's not necessarily true. Since the catch-all number could include anything it's not something they'd really be held to, but if they pass off ECC in specific figures people will probably cry foul when they learn it's false. It would have been okay if they said 8MB + 1MB ECC though.

What makes it less likely is that you don't tend to recalculate bytes based on ECC.. you just consider it to have 9-bit bytes. If they said something like 376 Mbits instead it'd be easier to believe they're including ECC.

Do we know what 28nm process Kabini is manufactured on?

I'm just wondering if it's 28nm HPM like the Xbox One SOC. I can't find anything on it. At least public, TSMC said that Snapdragon 800 was the first SOC to use the process.

Would not surprise me in the least if Temash/Kabini were HPM. Some of the design presentations go into detail about what the transistor mix is like and it's pretty varied. Where did TSMC say that Qualcomm was first?

 

[Gubbi]

The uncore bandwidth to the CPU section does look to be higher than some other Jaguar chips. Tweaking the uncore and L2 interface for higher bandwidth might be the reason.

They need to support coherency checks at full tilt, - even if the CPU block can't provide bandwidth enough for all the CUs; Cachelines need to be invalidated on GPU stores and need to serve data for read requests for lines is in a modified state. The 30GB bandwidth figure from the CPU block is in principle enough for four CUs for GPU compute with every access hitting the CPU block (which would be a data management FAIL for the developer)

I could also imagine support for packing/unpacking textures in various formats in the SIMD units, similar to what the 360 has.

Cheers

 

[-tkf-]

1.32 tflops, shouldn't that be higher with the raised clock?

 

[AlNom]

1.32 tflops, shouldn't that be higher with the raised clock?

(12*64)*2*853

 

[XpiderMX]

https://twitter.com/search?q=#Microsoft&src=hash

#Microsoft #Xbox One uses #Tensilica for audio and other cores I'm told here at #hotchips

https://twitter.com/rickbmerritt/status/372097331568857089
https://twitter.com/search?q=#hotchips&src=hash

 

[DrJay24]

56GB/s DRAM access from GPU for non-CPU cache coherent peak BW including coherent BW. Coherent BW is 30GB/s peak.

56GB/s or 30GB/s+26GB/s, or some combination between those. That doesn't seem like a lot to feed the eSRAM, what happened to the old 68GB/s number and where did the missing 12GB/s go?

Edit: Maybe I just can't see the numbers correctly, the 56 is really a 68?

 

[McHuj]

That's not necessarily true. Since the catch-all number could include anything it's not something they'd really be held to, but if they pass off ECC in specific figures people will probably cry foul when they learn it's false. It would have been okay if they said 8MB + 1MB ECC though.

What makes it less likely is that you don't tend to recalculate bytes based on ECC.. you just consider it to have 9-bit bytes. If they said something like 376 Mbits instead it'd be easier to believe they're including ECC.



Would not surprise me in the least if Temash/Kabini were HPM. Some of the design presentations go into detail about what the transistor mix is like and it's pretty varied. Where did TSMC say that Qualcomm was first?

Slightly ot:
http://www.tsmc.com/tsmcdotcom/PRListingNewsAction.do?action=detail&newsid=7581&language=E

 

[dobwal]

They need to support coherency checks at full tilt, - even if the CPU block can't provide bandwidth enough for all the CUs; Cachelines need to be invalidated on GPU stores and need to serve data for read requests for lines is in a modified state. The 30GB bandwidth figure from the CPU block is in principle enough for four CUs for GPU compute with every access hitting the CPU block (which would be a data management FAIL for the developer)

I could also imagine support for packing/unpacking textures in various formats in the SIMD units, similar to what the 360 has.

Cheers

I thought the 30GB of coherent bandwidth is referring to bandwidth available to the "system" ram. A cache hit goes over a bus (probably onion) with only 10-15 GB of bandwidth.

 

[dobwal]

56GB/s DRAM access from GPU for non-CPU cache coherent peak BW including coherent BW. Coherent BW is 30GB/s peak.

56GB/s or 30GB/s+26GB/s, or some combination between those. That doesn't seem like a lot to feed the eSRAM, what happened to the old 68GB/s number and where did the missing 12GB/s go?

Edit: Maybe I just can't see the numbers correctly, the 56 is really a 68?

What? I thought it was 30 GBs of coherent bandwidth to system ram and 38 GBs (I guess) over what I am guessing is garlic?

 

[DrJay24]

What? I thought it was 30 GBs of coherent bandwidth to system ram and 38 GBs (I guess) over what I am guessing is garlic?

That is what I'm trying to figure out, but the image looks more like "56GB/s" than "68GB/s".

 

[dobwal]

That is what I'm trying to figure out, but the image looks more like "56GB/s" than "68GB/s".

You might be right but the coherent bandwidth above doesn't look like "30". The numbers are pretty blurred on that end of the slide.

 

[BRiT]

#Microsoft #Xbox One uses #Tensilica for audio and other cores I'm told here at #hotchips

https://twitter.com/rickbmerritt/status/372097331568857089

Their website is http://tensilica.com/

 

[Rangers]

363mm^2 isn't bad. Makes the ESRAM decision look better.

Also 204 GB/s is monstrous. This thing will definitely have an edge in some areas.

 

[Bagel seed]

Here's a better picture. From pcworld

http://images.techhive.com/images/article/2013/08/xbox-one-gpu-diagram-100051501-orig.png

It's 68gb/s

 

[DrJay24]

Thanks. That angle really distorted it.

From the same PC World article.

One massive chip
Physically, the system-on-a-chip at the heart of the Xbox One is 363 square millimeters. But the real whopper is the amount of logic integrated within it: 5 billion transistors. Although Wikipedia isn’t necessarily the final arbiter, the Xbox One is possibly the largest chip manufactured to date

 

[Bagel seed]

I see S/PDIF out. I thought it was HDMI only?

 

[XpiderMX]

I see S/PDIF out. I thought it was HDMI only?

S/PDIF output is there since the reveal

 

[Bagel seed]

S/PDIF output is there since the reveal

I remember bkilian said something about not having to support some audio output and it was beneficial for audio latency? I guess that was analog then.