Xbox One (Durango) Technical hardware investigation

[BeyondTed]

TSMC 28 nm 6T SRAM

Per IBM, the CPU is built on a 45nm SOI process.
I haven't found an official statement as to the exact process the GPU uses, other than a non-descript 40nm process. There are eDRAM or similar memory types for that node besides IBM for those nodes, and no SOI process. The type of eDRAM wouldn't match what IBM uses for its processors.


A few things have changed since six years ago.
Chartered was acquired by Globalfoundries, and Durango was confirmed to be manufactured on a 28nm process.

This is alliance I'm speaking of, with a copyright date of this year.
http://www.commonplatform.com/

The following report shows what TSMC 28 nm 6T SRAM looks like.

(I still think 1T-eSRAM makes more sense, but this article is interesting about the other possible SRAM types. Still looking for 1T-SRAM references in 28nm)

http://www.chipworks.com/blog/technologyblog/2012/12/11/a-review-of-tsmc-28-nm-process-technology/

If you go to the link you can see a picture of the SRAM.


The FPGA manufacturers do not make extensive use of high density SRAM in their chip designs. Here we look to AMD’s graphics division and nVidia – both early adopters of TSMC’s new process technologies. Their graphics processing chips incorporate large amounts of high density 6T-SRAM. We usually find that AMD/ATI or nVidia are the first chips to market using the full feature set of TSMC’s advanced technologies, including high density SRAM.

Earlier this year, we completed a limited analysis of the high density SRAM on the AMD RadeonTM HD 7970 215-0821060 graphics processor, which was fabricated with TSMC’s HP process. Our TEM analysis confirmed the 215-0821060 transistor structure was identical to that seen in the Altera Stratix V device, as would be expected since both are based on the TSMC 28 nm HP process. The 215-0821060 features a 0.16 µm2 6T-SRAM with the transistors arranged in a uniaxial layout. By contrast the 90 nm ATI 215PADAKA12FG graphics processor extracted from ATI Radeon X1950 Pro Graphics Card had a SRAM cell that is over five times bigger, at 0.86 µm2.

 

[BeyondTed]

Picture of Wide I/O eDRAM SiP (Sony PS Vita)

Picture of Wide I/O eDRAM SiP (Sony PS Vita):

http://www.chipworks.com/blog/techn...-ps-vita-uses-chip-on-chip-sip-3d-but-not-3d/

This is an interesting way to get wide I/O memory into a SiP (mounted right on top of the die).

At least no one can argue about this being in production. I imagine this could be done with SRAM too.



However I don't know how you would get the heat out of a big SoC with the wide I/O memory on top of it.

 

[3dilettante]

It's not eDRAM, it's DRAM that is manufactured with a process very different from what is used for the digital logic. The SIP attaches a DRAM module on top of the processor.

The same could be done with SRAM because microbumps and chip packages don't care what's in the chip.

I'm afraid I don't see the relevance for Durango. We have photographs of it not doing this, and I don't think Sony is interested in coaching Microsoft in the ways of complex physical packaging.

 

[BeyondTed]

It's not eDRAM, it's DRAM that is manufactured with a process very different from what is used for the digital logic. The SIP attaches a DRAM module on top of the processor.

The same could be done with SRAM because microbumps and chip packages don't care what's in the chip.

I'm afraid I don't see the relevance for Durango. We have photographs of it not doing this, and I don't think Sony is interested in coaching Microsoft in the ways of complex physical packaging.

Sure, I realize it is plain DRAM. I think Sony called it "Semi e-DRAM" or something like that.

The relevance is in terms of all the nay-says for any complex form of packaging such as the CoWoS and/or TSV. With CoWoS or even an interposer you could imagine wide I/O connection of DRAM and SRAM die with an APU. That was really my point, just that complex packaging is seen in consoles (portables) today. That's all.

And my point regarding my previous post about 0.16 um2 6T SRAM in TSMC 28 nm was that it is then 0.16 x 32 x 8 = 40.96 mm2, so only 8% to 10% of the area of the shown/photographed Xbox One SoC.

It is such a small % of the SoC due to the density of the SRAM. So I guess after looking at that chipworks report it could be said that 6T should be no issue. After all that was a picture from an in-production AMD GPU.

 

[BeyondTed]

MoSys 1T-SRAM Available At TSMC

Apologies for the double-post:


The linked article is a year and a half old, and there is evidence that it isn't Durango, besides it being confirmed with the Xbox One release that the SOC is on 28nm.

This LinkedIn page indicates Oban is a 32nm port of the Xbox360 SOC. Using eDRAM on SOI to finally get the daughter die on the same chip sounds like a good fit.
I believe that was posted somewhere back in the thread you got your link from.

So based upon a Semi Accurate Forum post from a few minutes ago it looks like 1T-SRAM is a possibility at TSMC (28 nm fab for AMD GPU and likely a possibility for Xbox One): (I think (but not sure) that it is called "logic based eDRAM" with a controller that makes it into 1T-SRAM or eSRAM):

Here are the links that were posted:

http://www.design-reuse.com/news/15...sram-embedded-memory-licensing-agreement.html

http://www.mosys.com/investors.php?page=pressRoomtxt&id=340701

 

[3dilettante]

The relevance is in terms of all the nay-says for any complex form of packaging such as the CoWoS and/or TSV.

The Vita is a data point in favor of the naysayers against TSV, since the tech is very non-ideal for high power designs and was done because TSV is difficult and not ready for prime time.
Heat dissipation and the lack of stacked DRAM that can fit enough memory in the area of the APU makes this a non-starter for the consoles.

We have pictures of what Durango's innards looks like, and it does not use this, which is why I don't see the relevance to a thread concerning Durango.

And my point regarding my previous post about 0.16 um2 6T SRAM in TSMC 28 nm was that it is then 0.16 x 32 x 8 = 40.96 mm2, so only 8% to 10% of the area of the shown/photographed Xbox One SoC.

I'm going to note that the area taken up by an SRAM array isn't just the SRAM cells at the ideal minimum cell size. We'd need to know what cell size was settled upon, and we'd need to know more about the interface, redundancy, and the area cost of other elements of the arrays. This can take up a significant amount of die area all on its own.

For example, the 2 MB cache arrays in Kabini take up about 7% of the die area of a 110mm2 chip.
The full details of that cache aren't known for comparison to the minimum cell size, but we see there is a continuum of density from a pure collection of cells and functioning data array that would take up 125mm2 if it were multiplied by 16 times.

There's a decent markup in space required to make an SRAM array functional. Until we get more details, such as a die shot, we won't know what design decisions were done differently between the two pools.


edit:

So based upon a Semi Accurate Forum post from a few minutes ago it looks like 1T-SRAM is a possibility at TSMC (28 nm fab for AMD GPU and likely a possibility for Xbox One): (I think (but not sure) that it is called "logic based eDRAM" with a controller that makes it into 1T-SRAM or eSRAM):

If I wanted to debate posters on Semiaccurate, I'd post there.

Here are the links that were posted:

http://www.design-reuse.com/news/15...sram-embedded-memory-licensing-agreement.html

http://www.mosys.com/investors.php?page=pressRoomtxt&id=340701

I don't see any numbers, and the most recent date is six years ago.
Is there anything addressing a process node in this decade?

 

[BeyondTed]

The Vita is a data point in favor of the naysayers against TSV, since the tech is very non-ideal for high power designs and was done because TSV is difficult and not ready for prime time.
Heat dissipation and the lack of stacked DRAM that can fit enough memory in the area of the APU makes this a non-starter for the consoles.

We have pictures of what Durango's innards looks like, and it does not use this, which is why I don't see the relevance to a thread concerning Durango.


I'm going to note that the area taken up by an SRAM array isn't just the SRAM cells at the ideal minimum cell size. We'd need to know what cell size was settled upon, and we'd need to know more about the interface, redundancy, and the area cost of other elements of the arrays. This can take up a significant amount of die area all on its own.

For example, the 2 MB cache arrays in Kabini take up about 7% of the die area of a 110mm2 chip.
The full details of that cache aren't known for comparison to the minimum cell size, but we see there is a continuum of density from a pure collection of cells and functioning data array that would take up 125mm2 if it were multiplied by 16 times.

There's a decent markup in space required to make an SRAM array functional. Until we get more details, such as a die shot, we won't know what design decisions were done differently between the two pools.


edit:


If I wanted to debate posters on Semiaccurate, I'd post there.


I don't see any numbers, and the most recent date is six years ago.
Is there anything addressing a process node in this decade?

What if MS put the memory under the APU in a stack? Heat out the top, wide I/O through the bottom. Unlikely but interesting maybe.

As for six years ago I think that would be when much of the 32nm work kicked off at TSMC. So the decade ago comment seems off the mark.

As for Semi Accurate it related to a comment you made about the eDRAM being 32 nm. So I found a posting at Semi Accurate about a TSMC (28 nm fab) partner with 1T-SRAM. I am not particularly interested in whether or not you want to debate posters on Semiaccurate.

 

[3dilettante]

What if MS put the memory under the APU in a stack? Heat out the top, wide I/O through the bottom. Unlikely but interesting maybe.

Why do they need to? By your own math, and even by my more conservative math, it's possible to fit a big SRAM pool on the die we do see.
Doing that (stacking) would require drilling through the memory layer because the APU has thousands of pins to the outside world, and TSV is not ready. Heat also does not just go out the top. The APU now has a heater sitting under it, and some amount of heat does get carried down the lower connections.
At the very least, the heat generated below the APU is nearly 0 without an active and heat-sensitive IC sitting there worsening hot spots.

As for six years ago I think that would be when much of the 32nm work kicked off at TSMC. So the decade ago comment seems off the mark.

I asked for a source in this decade, and the TSMC 32nm node was cancelled.

As for Semi Accurate it related to a comment you made about the eDRAM being 32 nm. So I found a posting at Semi Accurate about a TSMC (28 nm fab) partner with 1T-SRAM. I am not particularly interested in whether or not you want to debate posters on Semiaccurate.

There is a difference between two corporations having an agreement, and that agreement applying to all parts of those corporations.
TSMC sells products on many nodes, and that release is so old that the 55nm and 40nm TSMC nodes were still in the future, much less the cancelled 32nm and actually realized 28nm node.

By the way, on a fuzzy memory, I managed to track through wiki to the November 2012 10-Q filing that Mosys has focused all its efforts on a specific IC product line for networking processors, which runs against the IP business that would be licensing 1T SRAM. This decision was made after the licensing business began to dry up.

http://www.mosys.com/investors.php?page=secfilings

Historically, our primary business has been defining, designing, marketing and licensing differentiated embedded memory and high-speed parallel and
serial interface intellectual property (IP) for advanced systems-on-chip (SoC) designs. However, our competitiveness and the demand for licenses to our IP have
declined since the beginning of 2011 when we began dedicating more of our engineering and marketing resources to our IC efforts. This trend is continuing, as
we place all of our ongoing business emphasis on IC product sales rather than on IP transactions.

I suppose this doesn't rule out buying a license a few years ago and hamstringing future portability to new processes, but I think it might be a risk factor to avoid.

 

[Kb-Smoker]

Sorry for the cross-pollination here but this is just breathtaking:

From mrcteam:











No wonder there is so much interest in "special sauce hidden in watts" talk going on there.

Mind you I post this not to mock but praise as there has been several weeks of 'data' to back this up:



I understand to a certain extent that fans of the console want it to be a "better Google-TV"+ the bestest next gen console + windows 8-ish PC all in one package but as good as MS engineering is I just don't think you are going to get this SuperBox.

Choices were made to make a hybrid device that brings you a next gen console experience and they seem to be pretty good choices ( leaving aside the yield/clock issues ) when it comes to balancing "regular computer code" and gaming code all in the same package. Running a next gen game in a VM is gonna be quite a feat and I can imagine that they are going to cost the crap out it over time ( don't they say they want to sell a billion of these things ).

Let's not forget the power of the cloud. Let's not forget the billion dollars spent on acquiring exclusive content for games, plus whatever big deals they can make with cable/movies/whathaveyou.

MS is going up against Apple as much Sony at this point. Why can't the special sauce be Microsoft's marketing budget ?

Wow...

I was just reading these crazy posters. I take back my comment about wuu. 2.0.... this amount of crazy is taking it to a whole new level.

But really I think these guys are just trolling people. The stuff is clearly wrong and wish Ted wouldn't bring this nonsense here.

Hope we get some more info at e3 because I can't this much crazy.

 

[Cyan]

It's not eDRAM, it's DRAM that is manufactured with a process very different from what is used for the digital logic. The SIP attaches a DRAM module on top of the processor.

The same could be done with SRAM because microbumps and chip packages don't care what's in the chip.

I'm afraid I don't see the relevance for Durango. We have photographs of it not doing this, and I don't think Sony is interested in coaching Microsoft in the ways of complex physical packaging.

Again, not much relevance for Durango, but maybe somewhat related.

I don't know if it's due to the eDRAM of Haswell, but Intel is having problems with the retail versions of Intel Core i Haswell processors. They overheat easily and have poor overclocking. (thanks Herebus for the news)

http://www.pcpro.co.uk/news/382267/intel-haswell-hotter-and-slower-than-expected

 

[BRiT]

Because there will be people overclocking the Durango? Because Durango will use eDRAM instead of eSRAM? Because Durango will have 128Meg eDRAM? Because Intel designed Durango's CPU and GPU?

I just don't see the relevance.

And to be pedantic, Intel is not having any problems with retail Haswell processors. It's the folks trying to overclock that are having issues. That's a huge distinction.

 

[BeyondTed]

I'm going to note that the area taken up by an SRAM array isn't just the SRAM cells at the ideal minimum cell size. We'd need to know what cell size was settled upon, and we'd need to know more about the interface, redundancy, and the area cost of other elements of the arrays. This can take up a significant amount of die area all on its own.

For example, the 2 MB cache arrays in Kabini take up about 7% of the die area of a 110mm2 chip.
The full details of that cache aren't known for comparison to the minimum cell size, but we see there is a continuum of density from a pure collection of cells and functioning data array that would take up 125mm2 if it were multiplied by 16 times.

There's a decent markup in space required to make an SRAM array functional. Until we get more details, such as a die shot, we won't know what design decisions were done differently between the two pools.

So perhaps Vishera is a reasonable reference, however likely an overestimate (no tags, local memory versus cache):

http://www.guru3d.com/articles_pages/amd_fx_8350_processor_review,2.html

So the die size is 315 mm2, 1.2B transistors and 8MB L3.

http://www.anandtech.com/show/6396/the-vishera-review-amd-fx8350-fx8320-fx6300-and-fx4300-tested

My very rough estimate is 1/5 to 1/4 die area for the L3. So yes, 32MB would be huge implemented that way. Close to 315 mm2 I must be overestimating from the photo.

That makes me wonder about 1T-SRAM again.

No, I have searched and found no 28 nm references. I still claim that if 32MB eDRAM can be put into the Wii U then an eDRAM based eSRAM (such as 1T-SRAM) might be a route. I can not comment on the foundry as I don't know which foundry is being used. I have to believe that IBM is not the only one who wants to try to get 1T going. I am not sure of the current status of that at AMD. I thought they wanted to also, but that is dated info. Can you update on more recent data? I expect TSMC would have interest in such a technology but I have not found any recent references yet. I will keep looking.



I am aware of the concept "there's a decent markup in space required to make an SRAM array functional":

http://beyond3d.com/showpost.php?p=1745746&postcount=3915

However I don't know the finer details and can't estimate the area needed.

 

[BeyondTed]

Why do they need to? By your own math, and even by my more conservative math, it's possible to fit a big SRAM pool on the die we do see.
Doing that (stacking) would require drilling through the memory layer because the APU has thousands of pins to the outside world, and TSV is not ready. Heat also does not just go out the top. The APU now has a heater sitting under it, and some amount of heat does get carried down the lower connections.
At the very least, the heat generated below the APU is nearly 0 without an active and heat-sensitive IC sitting there worsening hot spots.

I am not sure they need it, but I have a few questions after reading some 2012 Hot Chips conference information regarding large chips including some with large amounts of SRAM:

http://forwardthinking.pcmag.com/architecture/302169-high-end-server-chips-debut-at-hot-chips-12

For example, the 32 nm (not 28 nm but some what similar size node) Power 7+ chip pictured is 567 mm2 yet is only 2.1 billion transistors.

So I was wondering how 5 billion would fit on the admittedly already large Xbox One SoC shown in the wired photos.

Is the Power 7+ chip just much lower density? I would not think it possible to that extent at all.

The zNext chip (same reference/link) is 597 mm2 and 2.75 billion transistors.

So I was wondering how they fit 5 Billion transistors in. So I was wondering about stacking.

Now I have seen the high resolution wired photos and my guess (from the following post) is that it is showing the backside of one monolithic chip:

http://beyond3d.com/showpost.php?p=1747433&postcount=147



But it is a bit hard to tell as the thickness of the chip is a pixel or 2-3 in the wired high res photo. And I do not know what a stack would look like top down in a photo like that. I also don't think you could get the power out. But there is a graphic (which might be nothing more than a marketing graphic) showing three layers (CPU, GPU and eSRAM). Maybe it is just a marketing graphic and is symbolic only of the three main ingredients in the design.

http://compass.xboxlive.com/assets/1a/f8/1af8a351-41c7-4ab0-ab0c-1f4a8c9964ec.jpg?n=XBR_Image14.jpg

(Found on Semi Accurate Forum, sorry but it is normal to give some credit when you get the link/info from someone else.)

But I wondered what would happen if the GPU/CPU was a chip on the top of the board and then directly under the board with through board vias there was the huge eSRAM chip. Probably just non-sense but I wondered from the die size and transistor counts out of hot chips 2012 in 32 nm which is a close node size. Plus the symbolism of stacking in the MS picture.

Otherwise I wonder about 1T-SRAM to fit everything in. I don't doubt your position about 1T-SRAM on 28 nm, I simply would not know what each foundry has today and I thought AMD and others wanted that too, not just IBM:

I think it is called ZRAM but I have never seen it used (as far as I know) but AMD seems to have had interest at 45nm: (Yes, it is an old post. I'll look for something newer. But it mentions 45nm, not so horribly out of date.)

http://www.geek.com/chips/amd-licenses-zram-generation-2-564364/

Here are some quick specs:

Ultra-high density: greater than 5Mbits per square millimetre at 65nm, and greater than 10Mbits per square millimetre at 45nm (1.4 to 2x denser than eDRAM and 5 to 6x denser than SRAM)

High performance random array access: greater than 400MHz (when optimised for performance)

Very low active power consumption: under 10�W/MHz (when optimised for low-power)
So, to all of the anti-ZRAM zealots here at ChipGeek … be proud! Now you have a whole new chapter to mull over in your ramblings, one that might just demonstrate once and for all that ZRAM is actually all it's cracked up to be (or at least a fair sight closer to it than many originally thought).

All hail ZRAM! A memory architecture that could allow 10 MB caches on AMD64-based processors in the same footprint as a 2 MB cache would take up today. Boy, wouldn't that give AMD a rather large boon!

Maybe you have some understanding of what happened to ZRAM at AMD? Did the interest continue past 45 nm to 32 and 28? If not, what went wrong?

In March 2010, Innovative Silicon announced it was jointly developing a non-SOI version of Z-RAM that could be manufactured on lower cost bulk CMOS technology.
AMD has licensed the second generation Z-RAM [3] to research it for potential use in their future processors, but is not planning to start using it. [4]
DRAM producer Hynix has also licensed Z-RAM for use in DRAM chips.[5]
Innovative Silicon was closed on June 29, 2010.[citation needed] Its officers have left, and its patent portfolio was transferred to Micron Technology in December 2010.[6]

If AMD, Hynix and Micron showed interest there must be some truth/value in it. But not sure what the catch(es) are.

 

[Rangers]

Because there will be people overclocking the Durango? Because Durango will use eDRAM instead of eSRAM? Because Durango will have 128Meg eDRAM? Because Intel designed Durango's CPU and GPU?

I just don't see the relevance.

And to be pedantic, Intel is not having any problems with retail Haswell processors. It's the folks trying to overclock that are having issues. That's a huge distinction.

yeah it's nothing new, same problem with ivy bridge (without edram)

and people are still getting huge overclocks out of gpu's. probably 20-30% from a 1ghz baseline.

 

[3dilettante]

So perhaps Vishera is a reasonable reference, however likely an overestimate (no tags, local memory versus cache):

Kabini is a more reasonable reference, in my opinion. It's a 28nm Jaguar processor on a bulk TSMC process. Vishera is a totally different core on 32nm SOI process.
Kabini's description paints it as fundamentally the same processor (if not the exact same, as most indicates), same process generation, same substrate, same silicon performance targets, and potentially the same fab as Durango. I don't see the need to ignore a known example of Jaguar.

Adding a somewhat larger process node, totally different cores, different performance and reliability requirements, and SOI would bloat the area figure significantly.

No, I have searched and found no 28 nm references. I still claim that if 32MB eDRAM can be put into the Wii U then an eDRAM based eSRAM (such as 1T-SRAM) might be a route.

You can claim what you want. I haven't seen data presented that makes me find that claim compelling, and we have leaks and indirect indicators that the more mainstream memory solution is what was chosen.

I can not comment on the foundry as I don't know which foundry is being used. I have to believe that IBM is not the only one who wants to try to get 1T going.

The desire to have improved memory density is always present, but it has to be made workable for the economics of foundry customers, not IBM's server division. What will happen in the future is beyond the scope of the imminent release of Xbox One.

I am not sure of the current status of that at AMD.

They'll be able to choose from whatever their foundry of choice offers.

So I was wondering how 5 billion would fit on the admittedly already large Xbox One SoC shown in the wired photos.

Did Microsoft say 5 billion in the SOC, or 5 billion in the whole console product? There are other custom chips in the console Microsoft designed itself.

But there is a graphic (which might be nothing more than a marketing graphic) showing three layers (CPU, GPU and eSRAM). Maybe it is just a marketing graphic and is symbolic only of the three main ingredients in the design.

I believe you're correct that it's a symbolic marketing diagram.

I think it is called ZRAM but I have never seen it used (as far as I know) but AMD seems to have had interest at 45nm: (Yes, it is an old post. I'll look for something newer. But it mentions 45nm, not so horribly out of date.)

ZRAM has been discarded for some time.
They could never get it working reliably enough to make it viable.
AMD actually moved on to making PR announcements about another SRAM alternative in 2009 or so, but it has been unused and unmentioned for quite some time.

 

[SlickShoesRUCrazy]

Did Microsoft say 5 billion in the SOC, or 5 billion in the whole console product? There are other custom chips in the console Microsoft designed itself.

They were vague. They only said 5 billion transistors which they were likely talking about the entire console.

Its the same bs they tried to pull with the '200 GB/s of bandwidth' comment.

 

[Kb-Smoker]

They were vague. They only said 5 billion transistors which they were likely talking about the entire console.

Its the same bs they tried to pull with the '200 GB/s of bandwidth' comment.

Of course we can see right through it but fanboy run with this stuff. "it the biggest SOC EVER in a console"

If we didnt have the 768 ops per cycle comment then i bet we would have some of the craziness in here. That pretty much confirm the leak docs.

I hope MS lets the cat out of the bag tomorrow and just releases the complete specs like they did with the x360.

 

[BeyondTed]

They were vague. They only said 5 billion transistors which they were likely talking about the entire console.

Its the same bs they tried to pull with the '200 GB/s of bandwidth' comment.

It is that rumor which is obviously BS. There is a simple way to tell that the "combined bandwidth" rumor is obviously crap:

1. If the console contains the 768/7790 or any another of the other rumored variants of AMD GPU then you know that the combined bandwidth number would be in the TB/Second as those GPUs have had internal bandwidth like that for quite some time:

http://beyond3d.com/showpost.php?p=1745455&postcount=138

Aggregate bandwidth numbers for any recent AMD GPU are available in their OpenCL documentation.
For instance, for Pitcairn XT:
- 15360 GB/s to the register files
- 2560 GB/s to the local memories
- 320 GB/s to the constant memory
- 1280 GB/s to the L1 caches
- 512 GB/s to the L2 cache
Bandwidth to the L2 cache in GCN is bounded to the number of memory channels so I expect it to be 512 GB/s in the Xbox One.
Caches not relevant to GPGPU such as the ones inside the ROPs are not described in detail.

So a "summed bandwidth" number would need to be 20 TB/Second. So that rumor is the obvious BS here.



2. If the console contains 28 nm 6T SRAM (32MB) on the same chip then it is certainly vastly faster than the off chip eDRAM in the 360. That had 256 GB/s internal bandwidth. So there is no way a combined bandwidth number would be so incredibly low as 200 GB/s since the components are much higher BW than the 360 and the 360 combined BW was already well above 200 GB/s.

 

[Kb-Smoker]

It is that rumor which is obviously BS. There is a simple way to tell that the "combined bandwidth" rumor is obviously crap:

1. If the console contains the 768/7790 or any another of the other rumored variants of AMD GPU then you know that the combined bandwidth number would be in the TB/Second as those GPUs have had internal bandwidth like that for quite some time:

http://beyond3d.com/showpost.php?p=1745455&postcount=138



So a "summed bandwidth" number would need to be 20 TB/Second. So that rumor is the obvious BS here.



2. If the console contains 28 nm 6T SRAM (32MB) on the same chip then it is certainly vastly faster than the off chip eDRAM in the 360. That had 256 GB/s internal bandwidth. So there is no way a combined bandwidth number would be so incredibly low as 200 GB/s since the components are much higher BW than the 360 and the 360 combined BW was already well above 200 GB/s.

1. No that would be crazy. It just creative math to show the buses BW combined in the console. Saying 30 TB/s because you combine cache BW too is just silly. This doesn't disapprove anything.

2. Everything we have shows its not. Maybe we will get some more detail but a lot of this stuff is really silly. You may wish it was but we have to look at ths info we have in front of us. Its wishful thinking at best.

 

[Tap In]

well cboat on GAF just dropped his "Pre E3 OMG Trufhfact!" post and not one word about chips or clock speeds so have to assume dead rumor


...amongst a bunch of other anti-MS, Sony neutral info.