Will there be 300W Discrete GPUs in 5 years? 10?

[Entropy]

Whatever happened to that?
I remember being all excited as heck about the prospect of a giant 128MB L4 eDRAM desktop CPU
But they don't seem to have released a proper desktop version & all talk of eDRAM seems to be absent on Broadwell :|

Cost/benefit, I guess. I reckon that they assume that desktop users interested in better performing Graphics will opt for an add-in card rather than pay heavily for what is comparatively modest performance.
It is interesting that in Intels official list of processors, there are no Iris Pro products at all. http://ark.intel.com/products/codename/42174/Haswell#@All
I honestly don't know how to interpret this, it may be that those processors are only made available on request by corporate customers. These processors aren't found at online retailers either. Intel has made no sign that they will take any alternative path with Skylake, and since Cannonlake is supposed to be largely a process shrink of Skylake, this is how they intend to go forward until roughly mid 2018, if 10nm by beginning of 2017 was an accurate statement.
I guess their product stack is determined in discussions with their large customers influenced by their own long-term strategy.

Regardless, this opens a market window for AMD if non-upgradeable memory is acceptable, which it should be by many consumers, particularly given the benefits.

 

[Xmas]

An extra cache level is what Intel did with Crystalwell. It's arguably the most elegant solution, as it lets CPU cores use the embedded memory transparently.

But a simpler solution would be to make the stacked memory a separate pool, which would be fine for graphics, since drivers are already designed to manage a separate pool of VRAM. However, CPU cores wouldn't be able to access this memory, except by doing it explicitly, but history shows that very few people would bother. This solution would be sub-optimal, especially for HSA, but then again two channels of DDR4 dedicated to the (nearly) exclusive use of 4~8 CPU cores wouldn't be too bad.

If we're talking about several gigabytes of stacked HBM with external memory as an option (and some APUs might not offer that option at all, dropping the additional memory controller and I/O pins) I would expect them to be exposed as separate physical address ranges which the OS would manage transparently. The OS could provide allocation functions with explicit priority level, and treat ordinary allocations as medium priority which would be placed in HBM as long as there is space (but move them to external memory if there is a higher priority allocation, e.g. from the graphics driver).