whats the deal with powervr?

[arjan de lumens]

7-8Mtrans / 2 mm2 = 3.5-4 MTrans/mm2. That sounds WAY too high for 90nm. For comparison, consider that the G70 is about 300 Mtrans on 330 mm2, or about 0.9 MTrans/mm2 on 110nm - which, with perfect geometric scaling, scales to about 0.9 / (90/110)^2 = 1.3 Mtrans/mm2 on 90 nm.

Assuming 1.3 Mtrans/mm2, an area of 2 to 8 mm2 would suggest 2.6 to 10 million transistors. If each pipeline is as richly equipped as a G70 pipeline (??? a bit unlikely), this would suggest about 1 full-speed pipeline for the largest part.

 

[Farid]

We need a PVR icon! Dave! More icons.

With unified shaders and procedural geometry/HOS, where exactly are they one generation behind?

"Next-gen" Features set =/= "Next-gen" Performances.

And when you see House of the Dead 4, a game running on a closed and high cost (relative to a console and /or a PC GPU) Arcade system, I'd say that PVR Serie 5's performances are not exactly stellar...

Note that I assume that the Arcade board does use a PVR5 variant GPU, which has yet to be officially announced.

You seem to forget that there was a Series5 to be released last year.

Who knows? Finishing a design and being able to release it in quantity is two different things. Let's just look at Nvidia's NV30 and Ati's R520.

 

[TEXAN]

"Next-gen" Features set =/= "Next-gen" Performances.

And when you see House of the Dead 4, a game running on a closed and high cost (relative to a console and /or a PC GPU) Arcade system, I'd say that PVR Serie 5's performances are not exactly stellar...

"- Secondly, there's been some talk of HOTD4's graphics and people saying it looked a bit ropey.
You really shouldnt look at a static screenshot to judge a game nowadays, you probably missed the 200+ independantly animated zombies all reflected in a huge plate glass window running at you more like 28 days later, the fully destructable scenery and the most organic looking boss that rampages through the level destroying the level dripping blood as it chases you. It's far more impressive in motion than the screenshots imply, that and the fact that it's not even finished yet."

http://www.system16.com/

 

[Ailuros]

Who knows? Finishing a design and being able to release it in quantity is two different things. Let's just look at Nvidia's NV30 and Ati's R520.

IMG is not a fabless semiconductor manufacturer and never intended to become one. For mass-production obviously a partner would be needed.

http://www.beyond3d.com/interviews/pvrmbx/index.php?p=6

Last three questions/answers.

 

[mboeller]

7-8Mtrans / 2 mm2 = 3.5-4 MTrans/mm2. That sounds WAY too high for 90nm. For comparison, consider that the G70 is about 300 Mtrans on 330 mm2, or about 0.9 MTrans/mm2 on 110nm - which, with perfect geometric scaling, scales to about 0.9 / (90/110)^2 = 1.3 Mtrans/mm2 on 90 nm.

Assuming 1.3 Mtrans/mm2, an area of 2 to 8 mm2 would suggest 2.6 to 10 million transistors. If each pipeline is as richly equipped as a G70 pipeline (??? a bit unlikely), this would suggest about 1 full-speed pipeline for the largest part.

Thanks!

At least a first guess. But IMHO it could be missleading to use an highend chip from Nvidia as the base to judge the transistor-count of an small 3D-chip intended for PDA's and Northbridges.
Because of that I asked for the die-area of the RV350/RV380 chips because this chips are very small even compared with other lowend-chips from Nvidia for example. IMO this would give an better basis to roughly judge the transistor-count of the SGX.

As it seems the die-area of the RV350 is still unknown, or? At least we were not able to come to an conclusion back then. RV 350 die area

Based on that old calculations the SGX with 8mm² would have maybe ( 8/(0,278 x 200) x 75 x (130²/90²) = ) 22,5 Mio Transistors or 2.8 Mio transistors / mm²


So now we have three different figures

 

[Ailuros]

Uhmmm nothing against creative speculations for transistor counts, but if anything I wouldn't take neither RV360 nor G70 for reference.

Xenos might be a unified shader core but it's obviously lightyears apart from the necessities of the PDA/mobile market.

In any case a shader ALU on Xenos is a different beast compared to a G70 or RV360 ALU at least IMHLO; same should go for SGX too.

SGX is claimed to scale from 2 to 8 square millimeters die space and triangle performance to scale from 2M to 13.5M Polys/s; all of that at 200MHz if I haven't misunderstood anything. Without scaling the amount of ALUs I can't figure any other way out to scale performance.

Last time I checked when it comes to G70, it's 8 MADDs/clk for a PS ALU and 4 MADDs/clk for a VS ALU; what kind of "pipeline" do you folks take actually for reference?

 

[Jawed]

How much memory does the tile-triangle list in a TBDR consume? How does that compare with the memory required for an hierarchical-Z buffer?

Handheld versus desktop IGP versus desktop high-performance?

Jawed

 

[Ailuros]

How much memory does the tile-triangle list in a TBDR consume? How does that compare with the memory required for an hierarchical-Z buffer?

Handheld versus desktop IGP versus desktop high-performance?

Jawed

Who really knows exept PowerVR? Tiling has a hierarchical arrangement in a relative sense in their designs these days; since there's a macro tiling engine at the end of the SGX block diagram and there was a relevant patent issued years ago, it's safe to assume that they first break a scene up in macro tiles, in order to break those up in to micro tiles again.

On the ancient Series3/KYRO where those techniques weren't employed, the display list (if my memory serves me well) was less than 10% of the total available onboard memory. Bad comparison too, apart from the different techniques employed; I wouldn't expect them to not use any virtual memory at all by now and those are UMA devices.

 

[Jawed]

Ah well. I was hoping it might be the start of a comparison of relative die area consumed by memory (which I assume is more dense than general logic).

Jawed

 

[Fox5]

what about this: http://patft.uspto.gov/netacgi/nph-...,924,810.WKU.&OS=PN/6,924,810&RS=PN/6,924,810


It was already suggested that in 2007 AMD will release CPu with integrated video controller. AMD has 3 choices:
- do it themselves from scratch - do they have the needed resources ?
- ask one of big 2 - ATi/NV to do custom design, but then this won't be too different from what ATi/NV already sell
- ask one of small players wishing to take into desktops - PowerVR or Falanx ?!

Maybe by integrated video controller they meant the pciexpress bus controller?
More likely their Geode line would get integrated graphics.