What are the chinks in XB360's armour?

12-16 megs of eDRAM
Would have liked 33% higher bandwidth between CPU RAM AND GPU [ bump from 22GB to 33]
Larger L2 cache - 2MB minimum 3 MB preferable
VMXs that can handle their own threads much like the SPEs in Cell
Faster GPU ~ 700 MHZ

 

Acert93,
Well, I read the whole analysis, interesting read. Thanks. You should go work for McKinsey & Co. or something if you don't already. I think it's pretty much on the money, maybe I'd quibble with some rankings but that's basically how I see things shaking out as well. Anyway Shifty, sorry for hogging anymore of this technical thread, just wanted to give props to that market analysis which must have taken a 2 hours to write and is as good analytically as any Harvard MBA case study I've read. Now getting back to the technical stuff... [tries to push worms back in can]

 

I think 10MB was a good compromise on cost (and maybe die space)


Question: for L2 caches, is it just not possible to have 1.5MB? Some sort of thing against compromising between 1MB and 2MB?

 

i have to second blakjedi here - 10MB is not sufficient _given_ the mandatory targeted res of 720p, despite all the clever tiling. expect latency issues :?

 

Argh! When will people stop comparing the vmx units to SPEs? The VMX units couldn't "handle their own threads", then they wouldn't be VMX units anymore. The VMX unit is just a small part of the core, like the SSE unit in the P4 (I've never heard anybody suggest the SSE units should "handle their own threads")

It makes about as much sense as saying "I really wish the Opterons 16K bimodal global branch prediction counter could handle its own threads..."

sorry for ranting...

 

Won't a larger L2 also have a higher latency though? There's compromises in every choice a designer makes. Not to mention how much extra die space the extra 1-2MB would take up. It would be bigger than Cell. And producability wouldn't be very nice then.

 

ATI is on record as saying there wont be any performance penalties for 2x AA (2 tiles) and only 1-5% for 4x AA (3 titles... of course it seems the GPU can write to the eDRAM as it is also flushing the framebuffer to the main memory).

If those estimates from ATI are accurate it would seem that the process is pretty effecient. As tradeoffs go, I am sure there are other places of concern than a 1-5% drop at 720p with 4x AA.

 

Meybe Fast14 anuncement had gave to us to much hope, for ,at least, 2Ghz ALUs (at least the ALUs).

 

If you're assuming 4x FSAA at 720p, then you're talking around 18 MB. MSAA 2x, well, then 12 MB. Sans tiling, 10 MB is insufficient for antialiazing of any order.

1.5 MB of cache at least would have been good -- since it's shared among 3 cores, I think having only the equivalent of 340k of L2 cache per core isn't so much. At the very least, with 1.5 MB, you'd have at least 512k per core if it were evenly partitioned. Personally, I don't see what's the big deal about sharing the L2 cache, anyway.

 

Perhaps this has been mentioned (though I didn't see it), but I think the lack of a DVI port is a pretty major chink.

The xbox360 will end up connecting to most LCD or plasma HDTVs using component output, and some will probably end up using svideo or (dare I say it) composite. Having DVI means that there is atleast one more highend option for users with expensive TVs. There will be a greater chance that they will happen to actually use a high quality connection as opposed to something like composite.

Especially if you throw 1080p into the mix, DVI is going to play a big role.

Nite_Hawk

 

yes, i'm aware of what ATI are saying*. regardless, the only thing that can be carried out concurrently wrt EDRAM access is the zbuffer pass for the next frame while the last tile of the present frame is being flushed. unfortunately, the flushing of any prior tiles from the current frame is going to incur full penatly, and i can see absolutely no way to mask that.

* allow me to express my scepticism re ATI's claims: how can they claim 1-5% penaly at a certain tiling scheme if the tiling logic penaly is inherently _fixed_cost_ while the overall frame latency is arbitrary? how do they come up with the percentage figure? based on what frame timing?

 

That is opposed to what they have said. I distinctly asked and they are saying that writes can occur whilst the previous frame / tile is being resolved.

As for GDDR3 for system RAM - there is no more latency for GDDR3 than DR2, which is presently being employed by Intel systems (and AMD sooner or later). The system RAM on Xenos is alo running over twice as fast as current DDR2 system memories which would reduce the latency in relation.

 

Eight CPU's (ala Sun's Niagara chip) with 512 KB of exclusive cache for each CPU (4 MB total), and a segmented memory design with 512 MB for the CPU, and 512 MB for the GPU, with higher bandwidth (50 MB/sec) between the CPU and GPU would have been much better, so memory accesses would be less contentious. And of course a much higher capacity optical disk format.

Microsoft could have easily afforded that, and would have put them in a better position against it's rivals.

 

1) Most people dont need higher BW than that on thier internet. its useless for a console in most cases

2) You have got to kidding me about launch software. It has probably one of the strongest launch software lineup in gaming history.

3) Consumers feel nickled and dimeD at paying 299? I wonder how they will feel when paying 475 for PS3

4) 1080p is not needed until XBox 3

5) MS is playing it smart. Its primarily a software company and wants Windows to support whichever format will win, so its not supporting any outright

6) Developers always complain about memory latency, it doesnt effect system at all

7) MoreDevelopers than Xbox 1 are supporting Microsoft, Plain and Simple

8) No comment, thats stupid

9) Thats even more stupid

10) The Console is not a PC, and Console users want it that way, so the stupidest was left at the end
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This is how I read the article

Having said that you should work out what a flush costs (it hits peak bandwidth to main RAM, and how many you could do in a frame. Remember you need 3 of them for 4AA at 720P.

One of the benchmarks it would be interesting to run is whether the double buffering the EDRAM is worth the additional tiling overhead it incurs. I'd guess it probably wouldn't be, but it'd be worth running the test.

 

previous frame or tile? that's essential. if it's frame, then that is in line with what i said - they can carry out zbuffer writes while the last tile of the prev frame is being resolved. if it's tile, and more imporantly not the last one of the frame, then i'd be very curious to know how they do it assuming that Xenos is still an IMR, i.e. its access within a tile is still random.

 

Just double buffer the tile......

half the memory is resolving/clearing the other half is being used as a tile. As I said in my previous post I wouldn't bet oin this being a win from a performance standpoint, but it might be.