The pros and cons of eDRAM/ESRAM in next-gen

[Strange]

Lately there is many paper from ISSCC 2014
especially from eSRAM/ SRAM technology.

I will posted 2 techical digest of 6T SRAM from both Samsung and TSMC
both are using 16/14nm process.

Why?, because it is a perfect time to ask numerous question, related Xbox one eSRAM.
Especially the big question regarding is Xbox One SRAM is 6T or what ?
Of course the first thing to do is estimating the area of Xbox one SRAM

For reference
Jaguar + Surrounding area = ~ 26 mm2
http://info.nuje.de/Jaguar_CU.jpg

X1 VS PS4 die shoot
http://images.anandtech.com/doci/7546/diecomparison.jpg

PS4 GPU Area is ~80mm2, PS4 total = 328mm2
http://www.extremetech.com/extreme/...u-reveals-the-consoles-real-cpu-and-gpu-specs

Based on above (Use above data we can extrapolated the SRAM area), or use Ruler tool (etc)
http://i.imgur.com/f8SYdYH.jpg
Xbox one SRAM area,as there is total 2 Area, certainly less than PS4 GPU or Xbox one GPU area.
Xbox one SRAM area , per AREA ~40 mm2 (abosolutely less than 45 or 50mm2)

And we believe this per AREA hold 16MB and the type is 6T
The Question is based on what ??
Most of the people that said Xbox One SRAM 6T,
did not even provide any comparison to SRAM technology of TSMC or Samsung or other.
or even paper or technical digest for comparison.

Now i provided the latest in 6T SRAM from both Samsung & TSMC.
Also based on these data, the density of TSMC 16nm is basically the same as Samsung 14nm FF

Samsung 128mbit (16MB)
6T SRAM, 14nm FF
-----> area : 75.6 mm2 <----
http://i.imgur.com/7exhOXk.jpg
http://i.imgur.com/FqRO9Il.jpg

TSMC 128mbit (16MB)
6T SRAM , 16nm
----> area : 42.6 mm2 <----
http://i.imgur.com/n1BsRob.jpg
http://i.imgur.com/XHZwWrQ.jpg

Now is it possible that Xbox one SRAM is 6T using area less than both examples ? and still using 28nm ?, you be the judge ....

Well, one of the issues with the 6T transistor is that it fits well with the 5 billion transistor figure Microsoft gave us.

32MB = 256 Mbits = 262,144Kbits= 268,435,456bits.

with a 6T transistor we're looking at 1,610,612,736 transistors. (1.6 Billion)
768 stream processors is about 1.7 billion or so
8 Jaguar cores are rumored to be at least 800 million transistors based on other AMD products

add these three up we have at LEAST 4.1 billion transistors, and at most 900 million to spare for other purposes.

So if it's not a 6T SRAM then it's hard to add up to the 5 billion number.

 

[Dave Baumann]

back in late April.

And I don't think that's surprising. Unless they're selling at least 500k a month, reducing production surely will happen. We projected ~1 million consoles per month way back in September, remember?

I read the conference call transcript, and as I pointed out before they did not make any distinction between XBOX 360 and XBOX One.

 

[AlNom]

but it is impossible the density @28nm is better than 14nm (14nm itself already >2x, real 14nm of course will be ~4x, but currently it is like marketing term )
i can provide more example.

Alright, so putting aside the overhead space in the test chip images or spacing between macros there (unspecified I/O?), what is it you are suggesting?

An 8T SRAM design would bloat things, sure.

 

[mosen]

I measured each eSRAM block size and each of them are around 32% bigger than each Jaguar cluster (you can use XB1 APU die size which is 363mm2 which leads to same result). I'm not saying that it isn't 6T, but is it possible to put 16MB SRAM (~35mm2 die size @ 16nm) on a 28nm APU?

 

[Lalaland]

I measured each eSRAM block size and each of them are around 32% bigger than each Jaguar cluster (you can use XB1 APU die size which is 363mm2 which leads to same result). I'm not saying that it isn't 6T, but is it possible to put 16MB SRAM (~35mm2 die size @ 16nm) on a 28nm APU?

I don't believe so, as part of the fabrication process there are numerous acid wash phases that would mitigate against putting any wafer through twice for two different processes. Wile I have heard of daughter chips being on two separate processes I've never heard of a single monolithic chip being made with elements from two different process nodes.

Quite apart from that I would imagine that you would need to double up on power circuitry and such as differing process nodes often require different voltage levels et al to function properly compared to their predecessors.

I'm sure someone with more chip design experience can clarify though but I would bet against a chip being fabricated on two different nodes.

 

[MrFox]

hmmm... a year and a half ago, I speculated about the die size required for ESRAM if it was standard 6T, and I ended up with 60mm2 to 80mm2 for an array that would be implemented for similar needs as the WiiU. I used the size of WiiU EDRAM at 40nm as a reference, combined with MoSys and IBM statements about the area required for EDRAM versus SRAM in similar applications. Then halved it for 28nm. It was crude, but doesn't it indicates it's perfectly possible to have 32MB 6T sram in 70mm2?

WiiU is 40mm2, eDRAM is usually 3x density, a shrink to 28nm is 2x.
40mm2 x 3 x 0.5 = 60mm2 (an optimistic figure)

What if WiiU has an impressive 4x eDRAM?
40mm2 x 4 x 0.5 = 80mm2 (a pessimistic figure)

 

[mosen]

hmmm... a year and a half ago, I speculated about the die size required for ESRAM if it was standard 6T, and I ended up with 60mm2 to 80mm2 for an array that would be implemented for similar needs as the WiiU. I used the size of WiiU EDRAM at 40nm as a reference, combined with MoSys and IBM statements about the area required for EDRAM versus SRAM in similar applications. Then halved it for 28nm. It was crude, but doesn't it indicates it's perfectly possible to have 32MB 6T sram in 70mm2?

By your logic:

20nm is a full node shrink from 28nm. Technology enables ~50% area shrink for digital logic and SRAM . I assume there is about 30% shrink from 28nm to 22nm or 1.43x increase from 22nm to 28nm. 1T-SRAM-Q (quad-density) claimed that is only about 10%-15% larger than eDRAM and around 4x smaller than traditional 6T-SRAM.

Crystalwell 128MB eDRAM size on 22nm is ~84mm2.
32MB eDRAM =~21mm2.

21mm2x3x1.43=90mm2 (too optimistic figure).
21mm2x4x1.43=120mm2 (far from reality figure).

Just for fun :smile::

1T-SRAM-Q about 10%-15% larger than eDRAM-->1.1x-1.15x
1T-SRAM 50% smaller than 6T SRAM-->2x
1.43x increase From 22nm to 28nm (or 30% shrink)--> 1.43x

21mm2x1.15x2x1.43=~69mm2 (which is the size of the 32MB eSRAM)

 

[shredenvain]

you mean shipped.

Also, stopping production is going to increase price per unit. Not to mention inventory costs.

We don't have a confirmation that XB1 costs less to manufacture than PS4, If anything, there are reports that XB1 is actually more expensive. So I don't think PS4 making money automatically means the XB1 is also making money.

Both systems are making a profit, it might be a small profit on each unit.
They where both designed to make a profit.

Also 5 million shipped Xbox Ones is 5 million sold. They arent sold on consignment by Walmart, Gamestop or Best buy.

 

[Silent_Buddha]

Both systems are making a profit, it might be a small profit on each unit.
They where both designed to make a profit.

Also 5 million shipped Xbox Ones is 5 million sold. They arent sold on consignment by Walmart, Gamestop or Best buy.

We don't know the situation with the XB1, however, for Sony, they only make a profit on PS4 AFTER either a subscription to PS+ or some software purchases. The console itself appears to be sold at a slight loss.

From TGS

Sony's Masayasu Ito wouldn't reveal exactly how much the company is losing with each PS4 sold, however he said that the company is expecting a profit "on an average user's initial purchase."

So, PS4 is definitely profitable, but the hardware is still sold for a slight loss.

Regards,
SB

 

[TheWretched]

We don't know the situation with the XB1, however, for Sony, they only make a profit on PS4 AFTER either a subscription to PS+ or some software purchases. The console itself appears to be sold at a slight loss.

From TGS



So, PS4 is definitely profitable, but the hardware is still sold for a slight loss.

Regards,
SB

That's not what Kaz Hirai said, though...

Maybe the TGS quote is too old for that, I dunno.

 

[Shifty Geezer]

So, PS4 is definitely profitable, but the hardware is still sold for a slight loss.

Outdated info as TheWretched links.

 

[Strange]

Both systems are making a profit, it might be a small profit on each unit.
They where both designed to make a profit.

Also 5 million shipped Xbox Ones is 5 million sold. They arent sold on consignment by Walmart, Gamestop or Best buy.

"Designed to make a profit" and "making profit" are two different things. Things go wrong.



It is known by default that Microsoft has quite a bit of inventory on their hands.

Note that we know that the 4 million and 5 million marks are "shipped" and not "sold" like the rest of the data figures.

If this graph made from official announcements are anything to go by, we have the fact that between January 20 and April 14th, which is a total of ~70 days they shipped 1 million units, which is less than 500k per month.

Also considering that they started shipping consoles around early September, hitting 2 million at early December means that they would have to ship everything by early November, at the latest mid-November, giving them a maximum of ~75 days to make 2 million units.

Considering that after January the "ship rate" rate is much lower than in late 2013, this means one of two things.

1. They cut production, which means price per unit will go up.
2. They held the production at the initial rate, but in turn they will have to have somewhere to place these "unshipped" consoles, which cost money. Price per unit also goes up.

Enough derailing though, it's turning into the sales thread..... back to eSRAM.

 

[JPT]

Also 5 million shipped Xbox Ones is 5 million sold. They arent sold on consignment by Walmart, Gamestop or Best buy.

I expect that depends on the deal with the retailer.
For instance 60 days credit and maybe stock return/rotation deals, means that they are in stock at the reseller without having been payed for.

 

[mosen]

I did some calculation and it leads to a strange result. I used this parts of kotakaja post (here):

For reference
Jaguar + Surrounding area = ~ 26.2 mm2
http://info.nuje.de/Jaguar_CU.jpg

TSMC 128mbit (16MB)
6T SRAM , 16nm
----> area : 42.6 mm2 <----
http://i.imgur.com/n1BsRob.jpg
http://i.imgur.com/XHZwWrQ.jpg

And this cliam that 1T-SRAM is 2x smaller than 6T-SRAM. First I calculated the area only for 128kb SRAM macros (1024 SRAM macros) and then all area for SRAM macros for XB1 eSRAM (but still there are some spacing between macros on XB1 that I didn't calculate) like this:

Spoiler

1024 SRAM macros area on 16nm SRAM: ~20mm2
16MB XB1 SRAM without spacing between each 1024 SRAM macros block: ~33.78mm2

20mm2 x (28/16)^2 x 0.5 = ~30.6mm2

So as you can see it's ~3.1mm2 smaller than 4 SRAM blocks area which is consistent with our expectation. I nearly reached same result by using crystalwell 128MB eDRAM size in this post which surely is less accurate (unknown spacing between macros) but at least suggest 1T-SRAM for XB1.

But then we don't know where to look after remaining ~1.3 billion transistors. So I was thinking that probably Microsoft puts 4 blocks of 8MB 6T-SRAM on XB1 APU (two of them on top of other two so we can only see two of them on die shot), is it possible?

 

[3dilettante]

And we believe this per AREA hold 16MB and the type is 6T
The Question is based on what ??

Well, it's called ESRAM for one thing, and we've gone many months now since Durango has been taken apart by Chipworks and the like and no major bombshells have been in evidence.
It's assumed 6T here primarily because it's the most common one to use and it plays nicer with the given transistor counts.

A deviation from the routine could have been noteworthy enough, but nothing has been noted.
I think that something beyond that, such as eDRAM or other technologies that are not offered on 28nm TSMC, would have been talked about.

Now i provided the latest in 6T SRAM from both Samsung & TSMC.
Also based on these data, the density of TSMC 16nm is basically the same as Samsung 14nm FF

It's also rather close to the density of the TSMC/Samsung 20nm. Both processes are using metal layers from the 20nm process, which significantly constrains density improvement. SRAM can usually eke out some density improvement, which Samsung at least has promised to the tune of 10-15%.

Now is it possible that Xbox one SRAM is 6T using area less than both examples ? and still using 28nm ?, you be the judge ....

This is taking a test chip with what seems to be a very loose testing configuration on an unreleased process that has significantly fallen short of the usual density curve.
It may readily have problems looking good against a density-optimized array on a mature 28nm process.
Excising the ESRAM block from the whole of Durango is likely giving it slight boost against the figures derived for a whole test module.

Crystalwell 128MB eDRAM size on 22nm is ~84mm2.
32MB eDRAM =~21mm2.

Running math on whole-chip measurements overly penalizes the denser technology in a comparison where we are purposefully extracting just the storage array from Durango. There is a high-speed IO interface and other elements necessary to a whole functional chip, and Intel gave a Mbit/mm2 value for its 128Mbit 22nm eDRAM macro:
17.5 Mbit/mm2.

http://www.realworldtech.com/intel-dram/2/

The math above misses this by a little over 25%.
The attempted capacity cut, absent a similar quartering of the interface and other components, would likely leave a roughly 37mm2 chip.

 

[mosen]

Running math on whole-chip measurements overly penalizes the denser technology in a comparison where we are purposefully extracting just the storage array from Durango. There is a high-speed IO interface and other elements necessary to a whole functional chip, and Intel gave a Mbit/mm2 value for its 128Mbit 22nm eDRAM macro:
17.5 Mbit/mm2.

http://www.realworldtech.com/intel-dram/2/

The math above misses this by a little over 25%.
The attempted capacity cut, absent a similar quartering of the interface and other components, would likely leave a roughly 37mm2 chip.

You'r right, if we assume TSMC's 28nm 6T-SRAM macro overhead being about 1.5x (which should be a norm for 6T-SRAM macros) then we have:

0.16µm2 x 32 x (1024)^2 x 8 x 1.5 = 64.42mm2

It fits nicely in XB1 eSRAM block. Also John Sell at Hot Chips conference said that half of 5 billion transistors are used for 47MB on-die storage.

 

[DuckThor Evil]

I read the conference call transcript, and as I pointed out before they did not make any distinction between XBOX 360 and XBOX One.

I think it's logical to assume the comment was either about The One or both Xbox consoles, but certainly One was part of it. It was worded as plural. The demand for 360 has imo followed a pretty natural curve and thus planning its production shouldn't have been a any sort of challenge, whereas the One has clearly under performed their expectations (dropping Kinect).

 

[Dave Baumann]

The comment was about drying the channel, however they would / will need to still be building XBOX One to fill the channel with Kinect less versions.

 

[MrFox]

Is the ESRAM part of the SoC going to be an asset when they are going to move to a smaller node?
I mean would ESRAM be capable of shrinking better than other parts of the chip?

 

[taisui]

the idea is that it'll shrink along with other parts of the chip, versus not being able to, that's just how it works, when it moves to a smaller process, everything shrink to that scale.

The premise of some parts on the same chip can shrink "better" than the other parts implies that some other parts will shrink "worse" relatively, hence this is logically meaningless sentence.