Nah, I doubt that: eSRAM is directly, quickly accessible from GPU, not CPU - CPU penalties to access it are high.
eSRAM is integrated in the GPU core (far right of the chip), as the chip layout clearly shows.
For sure, however, there must be some investment in the CPU/GPU ties to the NB zone (plus whatever arbitration mode/stuff they did use)
The existence of the crossbar that routes data to eSRAM block controllers or memory channels was already disclosed.
In part, this enables a mostly transparent mapping of accesses to the eSRAM or main memory based on properties assigned via page table after the initial setup.
Upping the peak numbers that in terms of the number of eSRAM blocks and memory clients does impact the GPU's internal crossbar, then the on-die interconnect that routes accesses to the necessary endpoints.
AMD's APU read and write paths are very wide for this class of chip.
Could you elaborate why that wouldn't have been possible? Even some chip engineer on the Hotchip conference video asked them about that in the context about yield/price optimization.
http://forum.beyond3d.com/showpost.php?p=1838012&postcount=7745
No realistic/worthwhile eDRAM manufacturer, and no mass-level production of a stacked large SRAM or DRAM chip for a SOC this size and TDP. This console generation came a few years early for stacked DRAM/2.5D, which isn't quite the same but appears more tractable than getting high-power chips in a stack configuration.
The PS Vita gets away with a stacked WideIO interface, but assuming Durango is ~100W TDP, there's a good chance that stacked solution burns as much or less power at peak compared to the larger chip at deepest idle, given that the Vita TV is rated at less than 3W max as a total unit.