ST-Ericsson Nova A9600: dual-core ARM A15, PowerVR Series 6

Discussion in 'Mobile Devices and SoCs' started by rektide, Feb 15, 2011.

  1. Arun

    Arun Unknown.
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    May I casually point those interested in small bits about the Rogue architecture towards sections 6.3 and 6.4.3?

    Also a specific bit value in 7.1 may be interesting although too much should not be read into it (and obviously MRTs are also supported on SGX, although whether they're exposed is another issue, and if that maximum number of bits was lower then that may theoretically cause certain issues).

    I think the document also makes quite clear that maybe (just maybe!) dependent texture reads are a performance issue on SGX and this is no longer the case on Rogue.
     
  2. Lazy8s

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    The difference in granularity of branching might indicate a larger change in the configuration of the design than I expected. Or I'm reading too much into it.
     
  3. Rys

    Rys Graphics @ AMD
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    Nope, you're not reading too much into it; Rogue's quite a bit different at the scheduling and execution level than SGX (and by that I mean it's brand new and completely different :runaway: )
     
  4. Lazy8s

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    Hence, "Rogue" is a fitting code name, then!
     
  5. french toast

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    That reads very awesomely indeed!!....I love B3D ♡♥♡
     
  6. Ailuros

    Ailuros Epsilon plus three
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    * A branch granurality of one is pitiful compared to what today's desktop GPUs are capable of. However considering power constraints many of the so far shortcuts mobile architectures took should be perfectly understandable.

    * Lowp or else INT10/8 are gone just as I suspected, since I would had been very surprised if Rogue wouldn't contain "scalar" SIMDs.

    * Mathematical lookups are redundant to avoid bottlenecks.

    * Dependent texture reads are no longer a headache (amongst others I assume).

    http://www.imgtec.com/powervr/sgx_series6.asp

    A "super-threaded" housekeeper then.
     
  7. JohnH

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    In what way would allowing arbitrary divergence without the SIMD penalty seen on modern desktop GPU's be pitiful?

    Note that there are penalties associated with flow control on SGX but they have nothing to with granularity.
     
  8. Ailuros

    Ailuros Epsilon plus three
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    The layman here thought that flow control and granularity are associated. Point taken, another lesson learned.
     
  9. Exophase

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    I don't think he meant pitiful the way you think he did (kind of a strange word choice IMO).. the improved flexibility is good. He must have been referring to the efficiency loss implied, hence why Series 6 seems to have reduced granularity.

    Given that Series 5 designs started with just a couple USSEs and were big on explicit SIMD instead of thread implicit - which has the obvious benefit of being able to get more work done per cycle with smaller data types - it's not surprising that they'd also start with full branch granularity. But then move away from it when the ALU requirements scaled a lot higher.

    I wasn't actually expecting the 8/10-bit explicit SIMD to be dropped. I assumed the 4x10-bit SIMD capability was necessitating 40-bit registers and carried some overhead due to that. Maybe limiting things to 3x10-bit wasn't worth it (I'm going to assume the 4x8-bit format didn't work that way natively), or maybe there's a much bigger cost in handling both an 8/10-bit fixed point format along with two floating point formats than there is in the traditional integer SIMD divisions.

    AFAIK IMG was the only company offering a faster 10-bit lowp option, kind of a shame to see it go.
     
  10. wishiknew

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    Surprising Lenna's in that PowerVR pdf.
     
  11. Lazy8s

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    She's a regular in these PowerVR texture compression articles (and TC articles in general, of course). Same with the parakeet(?).
     
  12. PixResearch

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    Lorikeet ;P
    (in before Simon says it)
     
  13. Helmore

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    That picture alone has an pretty decently sized Wikipedia article dedicated to it, in case you want to know more.

    Linky:http://en.wikipedia.org/wiki/Lenna

    What about that parakeet, or lorikeet you guys are talking about though?
     
  14. Rys

    Rys Graphics @ AMD
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    See Simon F's personal 3D pages. It's one of his references images used during the development of PVRTC.
     
  15. Simon F

    Simon F Tea maker
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    Err... I think you have that all back-the-front.

    Squawk!
     
  16. JohnH

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    Not sure how we'd reduce Rogue branch granularity to be less than '1'... ;-)
     
  17. Rys

    Rys Graphics @ AMD
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    Qubits!
     
  18. Ailuros

    Ailuros Epsilon plus three
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    Not all too bad since back to front is one of the TBDR strengths :lol: I should more often have such brainfarts since it seems to get most of you boys into one thread :wink:
     
  19. Exophase

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    I'm referring to more efficiency gained in OTHER areas by reducing branch granularity, I hope this is clearer now :p
     
  20. Ailuros

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