ST-Ericsson Nova A9600: dual-core ARM A15, PowerVR Series 6

Discussion in 'Mobile Devices and SoCs' started by rektide, Feb 15, 2011.

  1. rektide

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    Describing the 28nm A9600, which the press release says will sample in 2011:

    Here's the press release.. They appear to be converting to PowerVR from Mali.
     
  2. rektide

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  3. Lazy8s

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    ST-Ericsson, back on top of the game in 2012.
     
    #3 Lazy8s, Feb 16, 2011
    Last edited by a moderator: Feb 16, 2011
  4. darkblu

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    What are the chances of that silicon finding its way in the near-future SE handsets? Suddenly my good 'ol SE feels worn and torn : )
     
  5. Lazy8s

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    They're a lot like Samsung in that regard, with the handset unit choosing suppliers of their processors independent of SE's semiconductor platform side.

    While they won't have a better time to choose their own tech next year, they've made some odd choices in the recent past.
     
  6. Ailuros

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    If they'll execute accordingly. What was that again ST? :roll:
     
  7. Lazy8s

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    Running the core GPU above 400 MHz and the ALUs to some extent a lot higher, some of the performance figures might start to make some sense.
     
  8. Ailuros

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    You'd still need 12 TMUs@>400MHz to exceed the 5.0 GPixels/s mark. TMUs are anything but cheap in hw, rather the contrary; especially if the texturing capabilities of those exceed the DX10.1 level.
     
  9. Lazy8s

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    Yeah, I'm off. I didn't factor in the SoC in a larger context nor properly account for the rising demand for resolution in these devices.

    Nova A9600 should equip 8 TMUs clocked at 625 MHz. Other parts clocked higher.
     
  10. Ailuros

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    It'll lead to a dead end with this endless guessing game. In order for your scenario to work you'd end up with 64 ALUs (in order to sustain a 4:1 ALU:TMU ratio) with either 4 FLOPs/ALU at a higher frequency than 625MHz as you say or 8 FLOPs/ALU at a lower frequency than 625MHz.

    Not that I know anything but how about a triple core each with 4 TMUs and a >400MHz frequency across the core?
     
  11. tangey

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    If we start with metrics of the 543/544 core that we do know and look at the pure graphics performance:-
    @200Mhz 35M polys/s, 400M pixels/s (no overdraw).

    Is it too simplistic to say that 554 with its x2 pipes will do twice this i.e. 70M polys + 800M pixels/s. if so at an imaginary 600MHz, a dual core 554 would be hitting 420M polys + 4.8G pixel/s.
    (ignoring bandwidth issues that are probably a concern at that stage !)

    So is it not conceivable that a next gen rogue core could acheive somewhat less than those figures (350M polys and 5.2G pixels) using a single core @ 500Mhz ?, i.e. less than x2 the performance of a single core 554, but design for much higher frequencies, noting that it's likely that ST's fill rate includes an overdraw allowance.
     
    #11 tangey, Feb 18, 2011
    Last edited by a moderator: Feb 18, 2011
  12. Ailuros

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    Are you sure you wouldn't want to redo that match?

    Errr nope:

    http://www.stericsson.com/press_releases/NovaThor.jsp

    >5GPixels without overdraw, >13GPixels with overdraw according to ST always.
     
  13. tangey

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    Yeah, my bad, I got my no-overdraw/overdraw mixed up. assuming IMG is sticking with 2.5 overdraw allowance, 13G = around 5.2G raw pixel fill rate, which is what I was aiming for to start with.
     
  14. mboeller

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    Think of it as an HD6470 @ 650MHz.

    IMHO the 5,2GPixel (13GPixel with overdraw) point to 650MHz or 1300MHz. Otherwise the Series6 would be too big @ 28nm; or ST is using a 2MP config without mentioning it in the press release.


    According to Gipsel, one SP-block with 40 SPs measures 1,85 mm² (based on the latest Die-Shot of a Bobcat APU, you can find here: http://www.hardware.fr/art/imprimer/819/ ). The 8 TMUs add a little bit of area. Result: 3 mm² (as far as I have understood it: 40 SPs + 4 TMU)

    so at 40nm the 160 SPs + 8 TMU would need 1.85 x 4 + (3-1,85) x 2 = 9,7 mm²

    With 28nm this could be reduced to 4,8 mm².... unfortunately GPUs need more than only SP's and TMU's. ;)
     
  15. Ailuros

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    Unfortunately Fusion hasn't been designed either for smart-phone heights. I wouldn't expect by the way that all of the Rogue variants will be 100% DX11; there are probably quite a few X11 aspects that could be cut back due to being redundant in the embedded space and better dedicated to additional performance transistors.

    I'll let a bit of the speculation out that I currently have and the IMG folks can laugh their heart out as much as they want since I'm sure it'll be wrong, but at least more feasible than the senseless math based on something entirely different.

    Rogue/A9600 = "triple core"

    Per core:

    16 VecX ALUs
    4 TMUs
    120M Tris/s@450MHz

    16*10*0.45= 72 * 3 = 216
    4*450 = 1.8 * 3 = 5.4
    120*3*95% = 350
     
  16. Exophase

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    10 FLOPs per ALU.. is that 4x FMADD + 2 for something else?
     
    #16 Exophase, Feb 19, 2011
    Last edited by a moderator: Feb 19, 2011
  17. Ailuros

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    It's a scenario from the layman here. I just used reverse math starting from the TMUs and went from there to the ALUs.

    I'd like to stand corrected but I'd be very surprised if they've gone the Vec5 (or VLiW5) road after all; seeing that AMD went just recently from VLiW5 to VLiW4 it would sound strange. 5XT ALUs are already 4+1 which probably gives you a 9th FLOP in probably non3D applications. Since 16*10 boded very well with the other stuff I could guess that there's a 2nd unit this time around that could be used for GP stuff and add another FLOP.

    As I said I'm sure it'll be 100% wrong and the IMG folks are laughing in their fists heh :(
     
  18. Erinyes

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    Im curious as to when this would release, given that TI is the lead licensee and OMAP 5 is slated to be available in devices in H2 2012, when would the other licensees release?

    If Cortex A15 based SoC's are not going to be available before H2, that would mean the next gen SoC's (slated for release in early 2011) would either go with a dual or quad Cortex A9 on 28nm.
     
  19. Lazy8s

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    ST-Ericsson must be able to not only avoid ramping up the main CPUs much but to control consumption well even when they do ramp in order to offer that 2.5 Ghz configuration.

    With the amazing 5G+ tex/sec real world fill rate, the GPU is also apparently keeping to the higher standard of clock rate.

    The differentiation in approaches and implementation in SoC design is really accelerating now. When ST-Ericsson and IMG reveal their innovations for achieving this later this year, we'll have a better idea about the evolution of app processors in this space and the competitive landscape.
     
  20. Ailuros

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    Well Arun's speculations might be closer to reality than mine after all; it could very well be that GPU frequencies end up significantly higher under 28nm then I imagined so far.

    That's a weird revival Lazy8s by the way ;)
     
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