WaltC said:
You're suggesting that the Printed Circuit Board for PCIe bus interface is not an "active" component?....
Yes, exactly. PCBs are just a bunch of wires between multiple layers of plastics.
WaltC said:
I'm not sure what you think I'm saying, but what I'm saying is that there's a distinction between a gpu and the host-bus circuitry interface the gpu sits on--which is usually mounted on the same pcb the gpu is mounted on.
The bus interface unit is part of the GPU, it's on-die.
WaltC said:
By "pcb" I mean the circuitry extraneous to the cpu, but local to the same pcb, which defines the host-bus interface for the card (slot pins, etc., included.)
I'm still not sure which part you're referring to, are you referring to the flip chip carrier or substrate which the GPU die is affixed to?
WaltC said:
nV10, nV15, nV20, nV25, nV30, and now nV40 have all denoted some type of architectural if not generational gpu advance in succession. For nVidia to name an nV40 sitting on a PCIe pcb (as described above) "nV45" seems completely incongruent to me, as these numbers have always denoted gpus, not reference designs. Certainly, I have no objection to nVidia calling an nV40 gpu mounted on a PCIe pcb "nV45"--but then I wonder what nVidia will start naming its gpus afterwards...
I'd expect them to have different codenames for every different pin-layout of the substrate, regardless of GPU and HSI combination used.
WaltC said:
In case you still don't quite follow my vernacular here, when ATi shipped the R300 the company made it plain that the R300 vpu itself would have been perfectly at home sitting on any host bus from PCI 66-AGP x8, but that the limitation of the 4x-8x AGP reference-design cards actually sold was an electrical limitation imposed strictly by the 4x-8x host bus interface circuitry of the reference design chosen for R300 deployment. IE, the same R300 would have done just fine mounted on a pcb congruent with PCI66 electrical connectivity as it would on a pcb congruent with AGP x8 electrical connectivity
Quite frankly, I've never heard/read such comments from ATi, but it's conceivable that you could support all these modes with a single bus interface unit, as they're rather simliar. (PCI66 in that case probably equals AGP 1x without AGP texturing support)
WaltC said:
So, it's generally not a good idea to confuse the gpu/vpu with the local bus circuitry the pcb it sits on uses to electrically connect with the host bus. So, I say "PCIe pcb" only to cut down on wordy descriptions, and to denote the distinction between a gpu/vpu and the host-bus interface circuitry of the pcb it happens to be mounted on. Just trying to illustrate that there's technically no such thing as a "PCIe gpu/vpu" as far as I can see, just as R300 was no more PCI66-native than it was AGP x8 native, etc.
As I've written above, the bus interface unit is part of the GPU, it's on the GPU die, and the only function of the different pieces of PCB the die is affixed to is the channel the signals coming from/going to the die. R300 'talks' AGP to the outside world (at different speeds though, as you mentioned), as do R420 and NV40. For these designs, the outside world is the AGP interface of the chipsets northbridge.
Now for the NV45 design it's a little more complicated, nVidia implemented the HSI bridge on the same carrier as the NV40_GPU, so the NV40_GPU 'talks' AGP (at an accelerated rate) to this bridge and the bridge then 'talks' PEG to the PEG interface in the northbridge of the chipset.
Native PEG designs like RV370, RV380 and RV423 'talk' PEG to the outside world, no amount of PCB work can change that and the only way for them to communicate with an older chipset having an AGP interface would be through a translator, or bridge, somewhere in the signal path.
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